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TDA4VPE-Q1: Using USXGMII Ports on TDA4VPE-Q1

jang hyoun soo
Prodigy 40 points

Part Number: TDA4VPE-Q1

Hello.
Below is a message that two USXGMII ports can be used among the data sheet contents of TDA4VPE-Q1 and that SGMII3 & 4 can be used.

However, in the EVM circuit diagram below, the circuit is configured as (PROC184E2(002)_SCH.pdf) SGMII1 & 2.

Which port can I use to use 5gbps and 10gbps? 

 

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  • 0
    TI__Guru* 75730 points

    Hi,

    jang hyoun soo said:
    Below is a message that two USXGMII ports can be used among the data sheet contents of TDA4VPE-Q1 and that SGMII3 & 4 can be used.

    No. Only CPSW MAC Port-1 and MAC Port-2 alone supports 5G and 10Gbps via XFI/USXGMII interface, and rest of all ports supports only SGMII 1G/2.5G.

    jang hyoun soo said:
    Which port can I use to use 5gbps and 10gbps? 

    As mentioned above, you can use either MAC Port-1 or MAC Port-2.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    So, is the content below wrong in the data sheet?

  • 0 in reply to jang hyoun soo
    TI__Guru* 75730 points

    HI,

    jang hyoun soo said:

    So, is the content below wrong in the data sheet?

    As per Data sheet, TDA4xPE6 does not support SERDES2 lanes and TDA4xPE4 does not support SERDES0 and SERDES2 lanes.
    Additionally TDA4xPE4 has muxing limitations for PCIe and SGMII on available SERDES lanes.
    The SERDES and Mux limitations are captured in Pin Attributes Table "VPE4 APE4" column. According to Pin Attributes SerDes1 SGMII lanes are available for using from TDA4xPE4 but PCIe2 lanes are not available as IP supports only two instances of PCIe signals such as PCIe0, PCIe1.

    Attaching a screenshot from Pin Attributes section for your reference.


    Best Regards,
    Sudheer