Host Interrupt Mapping of the CIC---TMS320C6678

use the Data Manual of the C6678

Hi Clement Mesnier.

can you tell me where ? I can not find the mapping relationship on the 6678 datasheet.Does the host interrupt 3 means the CIC0_OUT3?thanks

Look around page 158

What are you trying to do ? Set up an EDMA transfer with interrupts (rather than polling) ?

Hi  Clement Mesnier

        I want to know the relationship between channel and host interrupt .for the datasheet of CIC said the The mapping of the channels to host interrupts is fixed (one-to-one mapping).on the page 158 of 6678 datasheet ,which one represent the channel and which one represent host interrupt?

        example cpintc write to the STATUS_SET_INDEX_REG to set a system interrupt,the system interrupt is 3,mapping the system 3 the channel is 3,then enable the host interrupt 3,I am confused about why the host interrupt have to be 3.so I want to figure out the relationship between channel and host interrupt.thanks

For example, if you are working with CIC0, "System interrupt" is the input of the CIC0; "Host interrupt" is the output of CIC0 and the input of C66x Core_n.

The system interrupt list of CIC0 is in the Table 7-39 of the C6678 data manual. The host interrupt list is in the Table 7-38 of the C6678 data manual as CIC0_OUT_n.

The system interrupt can be mapped to any channel in the CICn and the channel is fixed mapping to the host interrupt (channel_n is mapped to host interrupt_n) in the KeyStone chip-level interrupt controller.

So in the previous example (system interrupt3 --> host interrupt 3), it is trying to map the "EDMA3CC1 TC_ERRINT1" event to the CIC0_OUT(3+8*n), which is the input event 63 of the CorePac_n.

The system interrupt 3 is not limited to be mapped to host interrupt 3 only, it could be any host interrupt (channel) of the CIC.

Sincerely,

Steven

Hi Steven Ji

The system interrupt 3 mapping to channel 4,can i mapping channel 4 to host interrupt 3,or the number of channel and host interrupt have to be same?

and for this code,         hnd = CSL_CPINTC_open(1);

open a handle for CIC1, why can I run this project on core 1?the figure 7-29 on datasheet of 6678 said the output of CIC1 can not feed core 1.

thanks

Guoping,

1. The channel to host interrupt mapping is fixed (same number). So if you map system interrupt N to channel M, the system interrupt N is mapped to host interrupt M as well.

You can decide which CIC output (or input to CorePac) you want to use first and map that system interrupt to that channel.

2. If you are using CIC1, you can still run the code on any Core. But it will not be working correctly on Core1 based on the predefined system connection mentioned in the data manual.

If  you want to trigger interrupt on Core1, please use CIC0.

If you want to use CIC1, it will be working with Core 4~7.

Sincerely,

Steven

Steven Ji said:

For example, if you are working with CIC0, "System interrupt" is the input of the CIC0; "Host interrupt" is the output of CIC0 and the input of C66x Core_n.

The system interrupt list of CIC0 is in the Table 7-39 of the C6678 data manual. The host interrupt list is in the Table 7-38 of the C6678 data manual as CIC0_OUT_n.

The system interrupt can be mapped to any channel in the CICn and the channel is fixed mapping to the host interrupt (channel_n is mapped to host interrupt_n) in the KeyStone chip-level interrupt controller.

So in the previous example (system interrupt3 --> host interrupt 3), it is trying to map the "EDMA3CC1 TC_ERRINT1" event to the CIC0_OUT(3+8*n), which is the input event 63 of the CorePac_n.

The system interrupt 3 is not limited to be mapped to host interrupt 3 only, it could be any host interrupt (channel) of the CIC.

Sincerely,

Steven

Hi Steven,

I am still confused about how the event routes to a certain core, e.g. core2. 

according to your description, "EDMA3CC1 TC_ERRINT1" event can only be routed to core0, because we have  (system interrupt3 --> host interrupt 3), so it is trying to map the "EDMA3CC1 TC_ERRINT1" event to the CIC0_OUT(3+8*0), 0 means core0.

if we map (system interrupt3 --> host interrupt 11), then it is trying to map the "EDMA3CC1 TC_ERRINT1" event to the CIC0_OUT(3+8*1), 1 means core1.

if we map (system interrupt3 --> host interrupt 19), then it is trying to map the "EDMA3CC1 TC_ERRINT1" event to the CIC0_OUT(3+8*2), 2 means core2. and so forth.

Is my understanding correct?

I am also confused about the comments #7 on page 161,

what does "7 For CorePac0~3, it is CIC0 (interrupt number+16*n).  " mean?

Yang,

For the first part, what you said are correct. Different CIC outputs will be routed to different CorePacs based on the event tables in the data manual. So for the same system event, we need to plan to use the dedicated CIC output in order to route to the correct CorePac.

For the second question, there is typo in the footnote. It should be corrected as "n is core number" as we corrected in C6657 data manual. We will fix it in C6678 or other KeyStone data manuals in the next release.