Hyperlink interrupts

Hi Team Ti,

                  I need confirmation/information on the following.

1. CIC2 output pins [32 queue events and 32 secondary events] are mapped to Hyperlink_int_i[0].........Hyperlink_int_i[63].is this correct ?

2. So basically these CIC2 [INTC2] gets events from HYPERLINK Cable connector and maps the interrupts to hyperlink via Hyperlink_int_i[0].........Hyperlink_int_i[63]?

2. If device X is connected to device Y. when data transfer happens from device X to device Y [assume i set gensoft register at device X], the asserted pins will be transferring the Interrupt pulse through one of these 32 queue/ 32 secondary events at device Y. Can someone explain more on this?

3. I see VUSR_INT_O in CIC2 Table also. what purpose does it serve?

4. is Hyperlink_int_O pin is mapped to VUSR_INT_O pin ? 

Thanks

RC Reddy

RC Reddy,

1. You are correct about the vusr_int_o --> CIC0_out --> CPU interrupt mapping.

The HyperLink interrupt can only map to one core at one time since the channel/host interrupt mapping in CICn is one to one.

CIC0_OUT_64 is mapped to Core0 and CIC0_OUT_74 is mapped to Core1, etc.

2. The HyperLink event table is missing in the C6670 data manual. Only 32 CIC2 outputs are mapped to HyperLink. The other 32 are Queue Manager events.

Please refer to the Table 7-69 in C6678 data manual. The C6670 should have the similar table with CIC3 to be CIC2.

So the CIC2_OUT44 (vusr_int_0) is not connected tot he HyperLink event input. It is the output from HyperLink to the other masters (CorePac/EDMA, etc).

We will try to add the HyperLink event table for C6670 in the next release.

Hope it helps.

Hi StevenJi,      

                   Thanks for your quick reply and let me put [my doubt] in detailed here

1. device X =======hyplnk CABLE=======> device Y

2. hyplnk CABLE [physical HL5CABLE] inputs goes to CIC2 

3. CIC2 Outputs 32 lines to hyplnk and other 32 lines comes from queue manager.

4. point 3 based 32+32 lines feed Hyperlink_int_i[0]...Hyperlink_int_i[63]. [refer figure 2-15 in hyperlink data manual].

5. these 64 pins converge to interrupt pending set register which will generate hyperlink_int_0.

6. point 5 based hyperlink_int_0 goes to CIC0 as CIC INPUT EVENT AT 111.

7. Alternative to point 6, HL5CABLE itself outputs system interrupt to hit 111 at CIC0.

basically, i am tracing where the CICO 111 and CIC2 44, Hyperlink_int_i[0]...Hyperlink_int_i[63] and CIC2 inputs [32] and qm inputs [32] all meet. in a logical diagram flow. is this correct ?

i will be happy if you explain all points clearly with [all pins,events,cables,outputs taken care]

Thanks

RC Reddy

RC Reddy,

First of all, the HyperLink cable only includes the SerDes pins and LVCMOS pins shown in Table 2-1 and Figure 2-1 in the HyperLink user guide. The interrupt pins are not involved with the cable pins.

Within each single device (device X or Y), the 32 CIC2 outputs and 32 queue manager outputs are connected to the 64 HyperLink hardware interrupt input pins (Hyperlink_int_i[0-63]) internally on the chip level within the device.

For example, in device X, the 64 hardware interrupt inputs could be provided to the interrupt pending/set register in the local device if Intlocal=1. Or they can be converted to the interrupt packet to be sent out to remote device via SerDes pins of the HyperLink cable (from device X to device Y) if Intlocal=0.

The interrupt pending/set register also has the input from the remote interrupt packet (from device Y to device X) if int2cfg=1.

If int2cfg=0, the remote interrupt packet will generate interrupt to other interrupt set registers controlled by Interrupt Pointer Index/Value registers.

The output of the interrupt pending/set register is the Hyperlink_int_O which is connected to the CIC0 input event 111 in the local device as an interrupt source of CorePac.

Hyperlink_int_O is also connected to CIC2 input event 44, which could be one interrupt source of EDMACC0.

Let us know if that is the info you are looking for. Thanks.

Hi Steven,

               Thanks for explanation. One more doubt i have is,

there are 32 CIC2 outputs which feeds hyperlink_int_i, but who feeds the 32 inputs to CIC2 to generated corresponding 32 outputs ?

[0,1,2,3,.........31] === CIC2=>  Hyperlink_int_i [0,1,2,3............31]

Queue Manager i understand that 32 lines are drawn from hardware queue manager lines, so for the other 32 lines, queue manager can assert the lines which will feed hyperlink_int_i [32......63].

Thanks

RC Reddy

CIC2_OUT_8-39 are mapped to Hyperlink_int_i_0-31. 

Any input event of CIC2 could be the interrupt source of any output of CIC2. It depends on how you want to map the source input event to the output interrupt of CIC2.

For example, you can map CIC2 input event 49 (TINT4L) to CIC2_OUT_10. And TINT4L becomes the input event #2 (CIC2_OUT_10) of HyperLink interrupt.

Hi Steven,

                Thanks for your reply.

Let me re-iterate the question in  basic words [probably i wasn't able to explain myself in last post], the Input pins of CIC2 are connected to whom.

In other words, who is driving the input pins of CIC2 [please tell in context of hyperlink]

Tell me, physically who is connected to CIC2 input pins.

[ ?? ] ========> CIC2

Thanks

RC Reddy

Hi Steven,

                Thanks for answers/replies. I appreciate your quick responses.

Regards

RC Reddy

Hi, Steven,

        i have a problem about hyperlink interrupt packet  which confuses me a lot.

      1.     i send a hyperlink interrupt packet from 6670 to 6678,  with  int2cfg = 1 in 6678 side,  and  the specified core serive this interrupt correctly.  so this tells me my

configuration in 6670 is also correct for sending a interrupt packet.

    2. then, i  set int2cfg = 0 in 6678,  in this case the received interrupt packet  is supposed to write to chip level interrupt controller (according hyperlink user guide).

but  i  output  all the intc ralated memory  space  such as cic0-3 、corepacintc 、IFR、ICR、IER、ISR and find  nothing written by this interrupt packet.

And then i changed value of  mps、interrupt pointer value register , but got the same result.

       So ,what confuses me is how can i  control the address the hyperlink interrupt packet write in 6678( receiver ).  from the user guide it seems "interrupt pointer value

register"  and  mps  decide where the interrupt packet write,  but when i configure interrupt pointer value  register" with a address ,  it  is not written finally.

     WISH your reply,

                       sincerely kabalagala.