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C6712D Clk Jitter question

Other Parts Discussed in Thread: TMS320C6712D

               

From a customer:

"I was looking in the TMS320C6712D data sheet for ECLKOUT specifications.  The only spec’s that I found are on page 71 of SGUS055.  These spec’s seem to be for ECLKOUT based on ECLKIN.  In our case, we are using a 48 MHz oscillator attached to CLKIN.  We use the PLL to multiply the 48 MHz by 3 and run the DSP at 144 MHz.  We also use the PLL to divide the 144 MHz by 3 and attach that signal to ECLKOUT.

 

                The spec’s on page 71 seem to imply that is ECLKOUT is based on a 48 MHz ECLKIN, then the period jitter per spec of +/- 0.9 nanoseconds would result in +/- 4.3% jitter.  Is that true for ECLKOUT based on ECLKIN?

 

                Would the spec for ECLKOUT based on the PLL output have the same amount of jitter?"

  • Steve,

    I do not see anything about jitter on page 71 of SGUS055. And page 71 of SGUS055 looks a lot like page 69 of SPRS293b.

    It looks like they are assuming that the variation in cycle time is equivalent to a jitter spec. This is not true.

    It does not look like we offer a jitter spec for ECLKOUT for the TMS320C6712D.

    Regards,
    RandyP