Failed to enumerate TMDSEVM6670LE Rev. 4.0 using TMDXEVMPCI

Could you check what is the value of "FPGA_ICS557_SEL" on your EVM please?

I think ICS557_SEL=0 selects the local clock as PCIe reference clock and ICS557_SEL=1 selects the clock from AMC pin (clock from PCIe slot).

If you are using local clock on the EVM, the PLL should be able to be locked (PCIE_SERDES_STATUS=0x309) after power up.

I am wondering if you have another EVM to compare and see if anything wrong with the clock generator or PICe PLL on the board.

Hi Steven,

Thanks for the response.

According to the board Technical Reference Manual,  section 5.6.2: FPGA Configuration Registers Descriptions, I can see:

     Register Address : SPI Base + 50h
     Register Name : ICS 557 Clock Selection Control Register
     Default Value: 00h
     Attribute : Read/Write

     Bit 0: FPGA_ICS557_SEL : This bit can be updated by the DSP software to drive a high or low value on the FPGA_ICS557_SEL pin. FPGA will latch the BM_GPIO7 as the default value when power-sequence is finished.

     0 : FPGA_ICS557_SEL drives low

     1 : FPGA_ICS557_SEL drives high

So if we consider that SPI Base = 0x20bf0000 according to the TMS320C6670 memory map summary, the register's adress is  0x20bf0050 and its value is 0 in my case. That means that there is something wrong with the IBL?

Unfortunately, we don't have another EVM to compare with.

I think that I made some mistakes in my previous message...

I loaded the IBL symbol via JTAG and I made sure that this part of the iblinit was executed.

if (((dev_stat & BOOT_DEVICE_MASK)>>DEVSTAT_BOOTDEVICE_SHIFT) == PCI_BOOT_MODE) {
/* Write ICS 557 Clock Selection Control Register in the FPGA */
/* 1 : FPGA_ICS557_SEL s driven high */
DEVICE_REG32_W(DEVICE_SPI_BASE(0) + SPI_REG_SPIDAT0, FPGA_WRITE_REG_CMD(FPGA_ICS557_SEL_CTRL_REG,1));
chipDelay32(10000);
/* Reset SPI */
DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);

iblPCIeWorkaround();
/* Will never reach here */
}

I tried to wite 0 and 1 to the ICS 557 Clock Selection Control Register but the PLL still unlocked in both cases:  the core 0 is spinning in the check Wait for PCIe PLL lock loop 

while(!(DEVICE_REG32_R(PCIE_STS_REG) & 1));

Can I be sure now that there is something wrong with the clock generator or the PICe PLL?

Please double check if the PCIe power/clock domain has been enabled (the PCIe registers space should be accessible starting from 0x21800000).

And please refer to the EVM schematic and see if you could verify the output of the clock generator on board is 100MHz for PCIe reference clock (ICS557_SEL=0 case) and also if you have the 100MHz clock from PCIe slot to AMC pin (ICS557_SEL=1 case).

If the PCIe PLL could NOT be locked in either case while you have the correct clock input, then it is probably something wrong with the PCIe PLL itself.

The problem was the ICS557-08: the 2:1 multiplexer chip for PCIe. This chip allows the user to select one of the two HCSL or LVDS input pairs and fan out to one pair of differential HCSL or LVDS outputs.

http://www.icst.com/document/557-08-datasheet

As we can see in the datasheet, the pins 1, 10 and 11 should be fed with a 3.3V VDD but I can't see it! I can see the 100MHz for PCIe reference clock input as well as control signals driven from the FPGA but not the output clock as the the chip is not powered on...

How should I proceed now? We bought the board 1 month ago from the TI eStore.

Glad you locate the issue. Hope your board is still under warranty and please contact the TI eStore or sales distributor for the procedure.