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How to know that a group of EMIF reads or writes have finished in 6678

Johannes
Mastermind 6240 points


Hi,

I began testing the EMIF module and what I'm getting is that I start a group of N writes and the function EMIF_WRITE function returns before the N writes have been done by the EMIF module. So the code returns to main while the EMIF controller is performing the N writes (and it does all the N writes). Is this right? If it's right, how do I know that the N writes or reads have been done? Is there an interrupt or something like that?

Thanks

  • 0
    TI__Expert 6815 points

    Johannes,

    Are you using the DSP core or some other master? With the DSP, there is no real way of knowing whether the data has landed in hte EMIF external memory. With EDMA for example, you can get the return acknowledgement from the EMIF peripheral in the form of an interrupt pending register (IPR) event. This will indicate that EDMA has handed off data to the EMIF peripheral but not necessarily that the data has landed in the external memory.

    In either case, you could just quickly do a dummy write to the revision code and status register and then perform a dummy read before proceeding to any action that depends on the N writes to complete.

  • 0 in reply to Aditya
    Mastermind 6240 points

    Thanks Aditya,

    The master is the DSP, in a single core, single thread application. Let me know if I got what you said, even if I use EDMA I won't be able to know that all N writes have been done, just that the data was transfered to DSP EMIF memory space and that the writes will be done, right?

    One thing I didn't understand is what action is expected if I do a dummy write and read of the RCSR register, is this just to have a delay? Or doing this implies that the N writes have been completed?

    Thanks

  • 0 in reply to Johannes
    TI__Expert 6815 points

    Johannes,

    Your understanding is correct. There is no way for the DDR3 memory device to send an acknowledge return signal back to the DDR controller after the last word has landed inside the memory. There is a single path between the MSMC module and DDR3 controller to access both the DDR data space (0x80000000...) and the DDR config space (memory mapped register space). A dummy write + read back to RCSR will add a delay and ensure the previous DSP initiated write to DDR space has completed.