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McBSP - EDMA Interrupt

Other Parts Discussed in Thread: TMS320C6455, SPRC234

void initEdma(void)
{
    CSL_Edma3HwSetup            hwSetup;
    CSL_Edma3Obj                edmaObj;
    CSL_Edma3ParamHandle        hParamBasic;
    CSL_Edma3ChannelObj         chObj;
    CSL_Edma3CmdIntr            regionIntr;
    CSL_Edma3ParamSetup         myParamSetup;
    CSL_Edma3Context            context;
    CSL_Edma3ChannelAttr        chAttr;
    CSL_Edma3HwDmaChannelSetup  dmahwSetup;
    Uint32                      loopIndex; 
    CSL_Status           				status;
		unsigned long long					llTemp;


    //Module initialization
    status = CSL_edma3Init(&context);
    if (status != CSL_SOK) {
        printf ("Edma module initialization failed\n");   
        return;
    }

     // Intc module initialization 
    intcContext.eventhandlerRecord = EventHandler;
    intcContext.numEvtEntries = 10;
    CSL_intcInit(&intcContext);
 
    // Enable NMIs
    CSL_intcGlobalNmiEnable();
    
    // Enable global interrupts 
    CSL_intcGlobalEnable(&state);

    // Opening a intc handle for edma event 
    vectId = CSL_INTC_VECTID_4;
    hIntcEdma = CSL_intcOpen (&intcObjEdma, CSL_INTC_EVENTID_RINT0, &vectId , NULL);

	  hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
    if ( (hModule == NULL) || (status != CSL_SOK)) {
        printf ("Edma module open failed\n");    
        return;
    }

		gRcvTCC = CSL_EDMA3_CHA_REVT0;


		// Edma module setup
    dmahwSetup.paramNum = 0;
    dmahwSetup.que      = CSL_EDMA3_QUE_0;
    hwSetup.dmaChaSetup = &dmahwSetup;
    hwSetup.qdmaChaSetup = NULL;
    status = CSL_edma3HwSetup(hModule,&hwSetup);
    if (status != CSL_SOK) {
         printf ("Hardware setup failed\n");
         CSL_edma3Close (hModule);
         return;
    }

    /* Setup the DRAE masks
     */
    regionAccess.region = CSL_EDMA3_REGION_0;
    regionAccess.drae =   0xFFFF ;   
    regionAccess.draeh =  0xff0000;
    status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, &regionAccess); 
    if (status != CSL_SOK) {
        printf("Edma region enable command failed\n");
        return;    
    }

    /* Channel open */
    chAttr.regionNum = CSL_EDMA3_REGION_0;
    chAttr.chaNum = gRcvTCC;
    hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status);   
    if ( (hChannel == NULL) || (status != CSL_SOK)) {
        printf ("Edma channel open failed\n");    
        return;
    }

	 /* Get the parameter handle */
    hParamBasic = CSL_edma3GetParamHandle(hChannel,0,&status);
    if (hParamBasic == NULL) {
        printf("Edma get param handle failed\n");
        return;
    }

    /* Edma parameter entry Setup */
    myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
                                             CSL_EDMA3_TCCH_DIS, \
                                             CSL_EDMA3_ITCINT_DIS, \
                                             CSL_EDMA3_TCINT_EN,\
                                             gRcvTCC,\
                                             CSL_EDMA3_TCC_NORMAL,\
                                             CSL_EDMA3_FIFOWIDTH_NONE, \
                                             CSL_EDMA3_STATIC_DIS, \
                                             CSL_EDMA3_SYNC_A, \
                                             CSL_EDMA3_ADDRMODE_INCR,	\
                                             CSL_EDMA3_ADDRMODE_INCR);  
    myParamSetup.srcAddr = (Uint32)0x30000000; //McBSP Receive Address  
    myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(1,1);       
    myParamSetup.dstAddr = (Uint32)recvbuf; 
    myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0,0);     
    myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE (hParamBasic,0);
    myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);     
    myParamSetup.cCnt = 1;   

    status = CSL_edma3ParamSetup(hParamBasic,&myParamSetup);
    if (status != CSL_SOK) {
        printf ("Edma param setup failed\n");
        return;
    }
    
   /* Association of an EDMA event handler with the INTC routine */
    EventRecord.handler = &eventEdmaHandler;
    EventRecord.arg = (void*)(hModule);
    CSL_intcPlugEventHandler(hIntcEdma,&EventRecord);

    /* Enabling event edma  */
    CSL_intcHwControl(hIntcEdma,CSL_INTC_CMD_EVTENABLE,NULL);
    
    /* Hook up the EDMA event with an completion code function handler */
    EdmaEventHook(gRcvTCC, tcc13Fxn);  

    /* Enable interrupts */
    regionIntr.region = CSL_EDMA3_REGION_0;
  	llTemp |= (unsigned long long)1 << gRcvTCC;
    regionIntr.intr = _loll(llTemp);   
    regionIntr.intrh = _hill(llTemp);
    status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr);    
    if (status != CSL_SOK) {
        printf ("Edma interrupt enable command failed\n");
        return;
    }
     

    /* Manually trigger the channel */
    status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL);
    if (status != CSL_SOK) {
        printf ("Edma channel set command failed\n");
        return;
    }
}

Read through the EDMA3 for the C6455 McBSP input data (DRR).
In order to test the EDMA interrupt when data is entered in the McBSP.
McBSP Digital loop back mode (DLB) have been set.



Therefore,
McBSP output data (DXR) is passed to the input data (DRR).
At this time, the EDMA interrupt occurs.

// McBSP setup

 hMcbsp->regs->PCR = 0x00000f00;
 hMcbsp->regs->RCR = 0x7f040040;
 hMcbsp->regs->XCR = 0x7f040040;
 hMcbsp->regs->SRGR = 0x20400101;

 hMcbsp->regs->SPCR =  0x00c18001;


EDMA set up like the attached file.

But,
McBS input data (DRR) is not copied to the buffer of EDMA.
McBSP input data (DRR) have been confirmed.

Ask a code review.

TMS320C620x,C642x McBSP UART(spra633c).pdf note, but
C6455 of the CSL (EDMA3) version, and there is a difference.

Ask if the code sample is worth noting McBSP-EDMA Interrupt.

Thank you.

  • Jeong Sang Gi,

    Do you have the CSL provided for the C6455? It includes examples, including one for the McBSP and EDMA and interrupts.

    Please start with the supplied working example to run on your DSK6455.

    You are using the wrong application note, since it says it is for the C620x and C642x McBSP. The C645x McBSP is newer than that.

    Please go to the TMS320C6455 Product Folder ( <- link provided ) to find the CSL and correct documentation for this device.

    Are you using your own board or a DSK/EVM? Which board are you using?

    Regards,
    RandyP

  • Had been using the C6455 CSL.
    I did not see the EDMA-McBSP file for 4 days as the demon possessed.

    The EDMA interrupt for MCBSP (UART) has been resolved.
    Thank you.

    I would like to implement a UART in 8N1 mode (eight data bits, no parity bit and one stop bit)  interrupt.

    McBSP as UART, Digital loop back mode has been set up.
    Therefore, the UART transmit data will be received and read.

    However, the UART receive data is read incorrectly.
    Perhaps the the EDMA3 Channel Parameter Setting is invalid.

    Please check the EDMA3 Channel Parameter Settings.

    void main(void){
     ProcessTransmitData();

     initMcBSP();
     initEDMA3();

     ProcessReceiveData();
    }

    /*******************************************************************/
    /* void ProcessTransmitData(void)                                  */
    /*                                                                 */
    /* This function expands each of the 8-bit ASCII characters in the */
    /* transmit string "xmit_msg" into UART transmission 16-bit word   */
    /* and place them in the transmit buffer "xmitbuf".  In addition,  */
    /* 16-bit Start and 8-bit Stop framing words, respectively, are    */
    /* inserted before and after each of the ASCII characters in the   */
    /* buffer.                                                         */
    /*******************************************************************/
    void ProcessTransmitData(void)
    {
     int  i;
     short cnt = 1;
     unsigned char  xmit_char;
     unsigned short *xmitbufptr;
     
     /* point to Transmit Buffer */
     xmitbufptr = (unsigned short *)xmitbuf;

     for (i=0; i<(sizeof(xmitbuf)/sizeof(unsigned int)); i++)
     {
      xmitbufptr[i] = 0x0000; /* zero fill buffer */
     }

     xmitbufptr = (unsigned short *)xmitbuf; 
     
     /* Process data BYTES in xmit_msg[] and put in xmit buffer */
     for (i = 0; i < BUFFER_SIZE; i++)
     {    
         /*Get transmit character (one byte) from xmit_msg[] and put in xmit buffer*/
      xmit_char = xmit_msg[i];
     
      /* Process each BYTE of transmit character */
      for (cnt = -1; cnt < 10; cnt++)
      {
       if (cnt == -1)                       //start bit
        *xmitbufptr++  =  0x0000;
       
       else if (cnt == 8 || cnt ==9) //stop bit
        *xmitbufptr++  =  0xFFFF;
       
       else if (xmit_char & (1 << cnt))
        *xmitbufptr++ = 0xFFFF;
       
       else
        *xmitbufptr++ = 0x0000;
            
      } /* end for cnt */      
      
     } /* end for i */

     

    unsigned short recvbuf[0x0400]; 
    unsigned short xmitbuf[0x0400]; 

    /********************************Setup for Tx******************************/

        /* param setup */
        myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
                                                 CSL_EDMA3_TCCH_DIS, \
                                                 CSL_EDMA3_ITCINT_DIS, \
                                                 CSL_EDMA3_TCINT_EN,\
                                                 CSL_EDMA3_CHA_XEVT0, \
                                                 CSL_EDMA3_TCC_NORMAL, \
                                                 CSL_EDMA3_FIFOWIDTH_32BIT, \
                                                 CSL_EDMA3_STATIC_DIS, \
                                                 CSL_EDMA3_SYNC_A,\
                                                 CSL_EDMA3_ADDRMODE_INCR,\
                                                 CSL_EDMA3_ADDRMODE_INCR \
                                                );          
        myParamSetup.srcAddr = (Uint32)xmitbuf;
        myParamSetup.dstAddr = (Uint32)CSL_MCBSP_0_TX_EDMA_REGS;
        myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(?,?);      
        myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(?,?);    
        myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(?,?);     
        myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);    
        myParamSetup.cCnt = 1;

     

    /********************************Setup for Rx******************************/

    /* Param Setup */
        myParamSetup1.option = CSL_EDMA3_OPT_MAKE(FALSE,FALSE,FALSE,TRUE,\
                                                  CSL_EDMA3_CHA_REVT0, \
                                                  CSL_EDMA3_TCC_NORMAL,\
                                                  CSL_EDMA3_FIFOWIDTH_32BIT, \
                                                  CSL_EDMA3_STATIC_DIS, \
                                                  CSL_EDMA3_SYNC_A, \
                                                  CSL_EDMA3_ADDRMODE_INCR, \
                                                  CSL_EDMA3_ADDRMODE_INCR \
                                                 );          
        myParamSetup1.srcAddr = (Uint32)CSL_MCBSP_0_RX_EDMA_REGS;
        myParamSetup1.dstAddr = (Uint32)recvbuf;
        myParamSetup1.aCntbCnt = CSL_EDMA3_CNT_MAKE(?,?);      
        myParamSetup1.srcDstBidx = CSL_EDMA3_BIDX_MAKE(?,?);    
        myParamSetup1.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(?,?);     
        myParamSetup1.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);    
        myParamSetup1.cCnt = 1;         
     
    } /* end ProcessTransmitData */

     

  • Jeong Sang Gi,

    Are you basing this on our Application Note that describes methods for implementing a UART using a McBSP and EDMA3? Please reply with the name and revision of that app note, if you are using one.

    You did not include actual code, but have many '?' in your code. Please explain what you are trying to do and show the actual code, if you want someone to look at your code for an opinion on it.

    Generally, you should mark an E2E thread as Answered when the original question is answered. Then it is best to post any new questions on a new thread with a relevant title so people will know what to look at if they want to supply an answer, or what to look at if they are looking for an answer.

    Regards,
    RandyP

  • I'm sorry.

    The UART Code was written by the The TMS320C620x C642x McBSP UART (spra633c).
    McBSP-EDMA3 Interrupt refer to the C6455 Chip Support Libraries (sprc234) code.
    Two files will be attached.


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    /* TEXAS INSTRUMENTS, INC.                                         */
    /* Date Created: 06/22/2001                                        */
    /* Date Last Modified: 07/9/2001                                   */
    /* Source File: uart.c                                             */
    /* Original Author: Todd Hiers                                     */
    /* Author: Scott Chen                                              */
    /*                                                                 */
    /* This code describes how to initialize the C6000 McBSP to        */
    /* communicate with an UART.  By modifying the CHIP definition,    */
    /* this code can be used to run on 6x1x/6x0x/64x.  #if statements  */
    /* are included in this code which allow flexibility in different  */
    /* devices.                                                        */
    /*                                                                 */
    /* On 6x0x devices, DMA channels 1 and 2 are used to service       */
    /* McBSP 1 transmit and receive operations, respectively.  On      */
    /* 6x1x/64x devices, EDMA channels 14 and 15 are used to service   */
    /* McBSP 1 transmit and receive operations, respectively.          */
    /*                                                                 */
    /* For this example, a data string is being transmitted from McBSP */
    /* transmit (DX) to McBSP receive (DR).  Each bit of the 8-bit     */
    /* ASCII character is expanded into 16-bit UART transmission word. */
    /* Once being received, the 16-bit UART transmission words are     */
    /* compressed back to binary bits and ASCII form.                  */
    /*                                                                 */
    /* For the code to work, DX, DR, and FSR of McBSP1 are shorted     */
    /* together.                                                       */
    /*                                                                 */
    /* This code has been verified for functionality on 6711, 6202,    */
    /* and 6203 devices.                                               */
    /*                                                                 */
    /* This program is based on CSL 2.0.  Please refer to the          */
    /* TMS320C6000 Chip Support Library API User's Guide for further   */
    /* information.                                                    */
    /*******************************************************************/
    
    /* Chip definition - Please change this accordingly */
    #define CHIP_6711 1
    
    /* Include files */
    #include <csl.h>   
    #include <csl_mcbsp.h>
    #include <csl_edma.h> 
    #include <csl_dma.h>
    #include <csl_irq.h> 
    #include <stdio.h>
    
    /* Create buffers and aligning them on an L2 cache line boundary. */
    #pragma DATA_SECTION(xmitbuf,"xmit_buf");
    unsigned short xmitbuf[0x0400];	  
    
    #pragma DATA_SECTION(recvbuf,"recv_buf");
    unsigned short recvbuf[0x0400];		
    
    /* Definitions	*/ 
    #define BUFFER_SIZE	27				/* total number of UART data words	*/
    #define TRUE 1
    #define FALSE 0
    
    /* Declare CSL objects */
    MCBSP_Handle hMcbsp1;			/* handle for McBSP1  */
    #if (EDMA_SUPPORT)
    	EDMA_Handle hEdma14;			/* handle for EDMA 14 */
    	EDMA_Handle hEdma15;			/* handle for EDMA 15 */
    #endif
    #if (DMA_SUPPORT)
    	DMA_Handle hDma1;				/* handle for DMA 1 */
    	DMA_Handle hDma2;				/* handle for DMA 2 */
    #endif
    
    /* Global Variables	*/
    volatile int receive_done = FALSE;
    volatile int transmit_done = TRUE;
    char xmit_msg[BUFFER_SIZE] = "McBSP does UART on C6000!\n";
    char recv_msg[BUFFER_SIZE] = "Transmission didn't work!\n"; 
    
    /* Include the vector table to call the IRQ ISRs hookup */
    extern far void vectors();
    
    /* Prototypes	*/
    void ConfigMcBSP(void);
    void ConfigEDMA(void);
    void ConfigDMA(void);
    void ProcessTransmitData(void);
    void ProcessReceiveData(void);
    short VoteLogic(unsigned short);
    int CheckTestCase(void);
    interrupt void c_int11(void);
    interrupt void c_int09(void);
    interrupt void c_int08(void);
    
    
    /*******************************************************************/
    /* void main(void)                                                 */
    /*******************************************************************/
    void main(void)
    {
    	
    	int waittime = 0;
    	int works = FALSE;
    	
    	/* initialize the CSL library */
    	CSL_init(); 					
    	
    	/* enable NMI and GI */
    	IRQ_nmiEnable();
    	IRQ_globalEnable();
    	
    	/* point to the IRQ vector table */
    	IRQ_setVecs(vectors);
    
    	#if (EDMA_SUPPORT)	
    	
    		/* disable and clear the event interrupt */
    		IRQ_reset(IRQ_EVT_EDMAINT);
    	
    		/* clear Parameter RAM of EDMA */
    		EDMA_clearPram(0x00000000);
    		
    	#endif
    	
    	#if (DMA_SUPPORT)
    	
    		DMA_reset(INV);
    		
    	#endif
    	
    	/* process transmit data */
    	printf("Processing Transmit string...\n");
    	ProcessTransmitData();   
    	printf("String transmitted: %s \n", xmit_msg);
    
    	#if (EDMA_SUPPORT)	
    	
    		/* Open the EDMA channels - EDMA 14 for transmit, EDMA 15 for receive	*/
    		hEdma14 = EDMA_open(EDMA_CHA_XEVT1, EDMA_OPEN_RESET);
    		hEdma15 = EDMA_open(EDMA_CHA_REVT1, EDMA_OPEN_RESET);
    		
    	#endif
    
    	#if (DMA_SUPPORT)
    	
    		/* Open the DMA channels - DMA 1 for transmit, DMA 2 for receive */
    		hDma1 = DMA_open(DMA_CHA1, DMA_OPEN_RESET);
    		hDma2 = DMA_open(DMA_CHA2, DMA_OPEN_RESET);
    		
        #endif            
    	
    	/* Open the McBSP channel 1 */
    	hMcbsp1 = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);
    	
    	#if (EDMA_SUPPORT)
    		
    		/* Configure the EDMA channels */
    		ConfigEDMA();
    	
    		/* enable EDMA-CPU interrupt tied to McBSP */
    		IRQ_enable(IRQ_EVT_EDMAINT);
    	
    		/* enable EDMA channel interrupt to CPU */
    		EDMA_intEnable(14);
    		EDMA_intEnable(15);
    	
    		/* Enable EDMA channels */
    		EDMA_enableChannel(hEdma14);
    		EDMA_enableChannel(hEdma15);
    
    	#endif
    
    	#if (DMA_SUPPORT)
    	
    		/* Configure the DMA channels */
    		ConfigDMA();
    		
    		IRQ_disable(IRQ_EVT_DMAINT1);
    		IRQ_disable(IRQ_EVT_DMAINT2);
    		
    		IRQ_clear(IRQ_EVT_DMAINT1);
    		IRQ_clear(IRQ_EVT_DMAINT2);
    		
    		IRQ_enable(IRQ_EVT_DMAINT1);
    		IRQ_enable(IRQ_EVT_DMAINT2);
    		
    		DMA_start(hDma1);            /*start DMA channel 1*/                            
    		DMA_start(hDma2);            /*start DMA channel 2*/
    		
    	#endif
    	
    	/* Setup for McBSP */
    	ConfigMcBSP();
    
    	/* Start Sample Rate Generator: set /GRST = 1 */
    	MCBSP_enableSrgr(hMcbsp1);
    	
    	/* inserted wait time for McBSP to get ready */
    	for (waittime=0; waittime<0xF; waittime++);
    	
    	/* Wake up the McBSP as transmitter and receiver */
    	MCBSP_enableRcv(hMcbsp1);
    	MCBSP_enableXmt(hMcbsp1);
    	
    	/* Enable Frame Sync Generator for McBSP 1: set /FRST = 1 */
    	MCBSP_enableFsync(hMcbsp1);
    	
    	/* To flag an interrupt to the CPU when EDMA transfer/receive is done */
    	while (!receive_done || !transmit_done);
    
    	/* Check to make sure the test case works */
    	works = CheckTestCase();
    	if (works != 0) printf("Transmission Error....\n\n");
    	else printf("Received data matched transmitted data!\n\n");
    					
    	/* process received data */
    	printf("Processing Receive string...\n");
    	ProcessReceiveData();
    	printf("String received: %s \n", recv_msg);
    
    	#if (EDMA_SUPPORT)
    	
    		IRQ_disable(IRQ_EVT_EDMAINT);
    		EDMA_RSET(CIER, 0x0);
    	
    	#endif
    	
    	#if (DMA_SUPPORT)
    	
    		IRQ_disable(IRQ_EVT_DMAINT1);
    		IRQ_disable(IRQ_EVT_DMAINT2);
    		
    	#endif
    	
    	MCBSP_close(hMcbsp1);	/* close McBSP 1 */
    	
    	#if (EDMA_SUPPORT)
    	
    		EDMA_close(hEdma14);	/* close EDMA 14 */
    		EDMA_close(hEdma15);	/* close EDMA 15 */
    	
    	#endif	
    	
    	#if (DMA_SUPPORT)
    	
    		DMA_close(hDma1);	/* close DMA 1 */
    		DMA_close(hDma2);	/* close DMA 2 */
    	
    	#endif
    }	/* End of main() */
       
      		
    /*******************************************************************/
    /* void ConfigEDMA(void): set up EDMA channel 14/15 for UART Xmit  */
    /*******************************************************************/
    #if (EDMA_SUPPORT)
    
    void ConfigEDMA(void)
    {
    	EDMA_configArgs(hEdma14,
    
    		/* OPT Setup */	
    		#if (C64_SUPPORT)
    		  	EDMA_OPT_RMK(
    	 		EDMA_OPT_PRI_HIGH,		/* 1  */
    	 		EDMA_OPT_ESIZE_16BIT,	        /* 01 */
        			EDMA_OPT_2DS_NO,		/* 0  */
        			EDMA_OPT_SUM_INC,		/* 01 */
        			EDMA_OPT_2DD_NO,		/* 0  */
        			EDMA_OPT_DUM_NONE,		/* 00 */
        			EDMA_OPT_TCINT_YES,		/* 1  */
        			EDMA_OPT_TCC_OF(14),	        /* 14 */
    			EDMA_OPT_TCCM_DEFAULT, 	        /* 0  */
    			EDMA_OPT_ATCINT_DEFAULT,        /* 0  */
    			EDMA_OPT_ATCC_DEFAULT, 	        /* 0  */
    			EDMA_OPT_PDTS_DEFAULT, 	        /* 0  */
    			EDMA_OPT_PDTD_DEFAULT, 	        /* 0  */
    			EDMA_OPT_LINK_NO,		/* 0  */
        			EDMA_OPT_FS_NO			/* 0  */
      			),
      		#else
    		  	EDMA_OPT_RMK(
    	 		EDMA_OPT_PRI_HIGH,		/* 1  */
    	 		EDMA_OPT_ESIZE_16BIT,	        /* 01 */
        			EDMA_OPT_2DS_NO,		/* 0  */
        			EDMA_OPT_SUM_INC,		/* 01 */
        			EDMA_OPT_2DD_NO,		/* 0  */
        			EDMA_OPT_DUM_NONE,		/* 00 */
        			EDMA_OPT_TCINT_YES,		/* 1  */
        			EDMA_OPT_TCC_OF(14),	        /* 14 */
        			EDMA_OPT_LINK_NO,		/* 0  */
        			EDMA_OPT_FS_NO			/* 0  */
      			),  		
      		#endif
    		
    		/* SRC Setup */  		    
    		EDMA_SRC_RMK((Uint32) xmitbuf),        /*xmitbuf address*/
    		
    		/* CNT Setup */
    		EDMA_CNT_RMK(
    			EDMA_CNT_FRMCNT_DEFAULT,
    			EDMA_CNT_ELECNT_OF(BUFFER_SIZE*11)
    		),
    		
    		/* DST Setup */
    		EDMA_DST_RMK(MCBSP_getXmtAddr(hMcbsp1)),
    		
    		/* IDX Setup */
      		EDMA_IDX_RMK(0,0),
      		
      		/* RLD Setup */
      		EDMA_RLD_RMK(0,0)
    		);
    
    	EDMA_configArgs(hEdma15,
    		
    		/* OPT Setup */
    		#if (C64_SUPPORT)
        		EDMA_OPT_RMK(
    	 		EDMA_OPT_PRI_HIGH,		/* 1  */
    	 		EDMA_OPT_ESIZE_16BIT,	        /* 01 */
        			EDMA_OPT_2DS_NO,		/* 0  */
        			EDMA_OPT_SUM_NONE,		/* 00 */
        			EDMA_OPT_2DD_NO,		/* 0  */
        			EDMA_OPT_DUM_INC,		/* 01 */
        			EDMA_OPT_TCINT_YES,		/* 1  */
        			EDMA_OPT_TCC_OF(15),	        /* 15 */
    			EDMA_OPT_TCCM_DEFAULT, 	        /* 0  */
    			EDMA_OPT_ATCINT_DEFAULT,        /* 0  */
    			EDMA_OPT_ATCC_DEFAULT, 	        /* 0  */
    			EDMA_OPT_PDTS_DEFAULT, 	        /* 0  */
    			EDMA_OPT_PDTD_DEFAULT, 	        /* 0  */
        			EDMA_OPT_LINK_NO,		/* 0  */
        			EDMA_OPT_FS_NO			/* 0  */
      			),
      		#else
        		EDMA_OPT_RMK(
    	 		EDMA_OPT_PRI_HIGH,	        /* 1  */
    	 		EDMA_OPT_ESIZE_16BIT,	        /* 01 */
        			EDMA_OPT_2DS_NO,		/* 0  */
        			EDMA_OPT_SUM_NONE,		/* 00 */
        			EDMA_OPT_2DD_NO,		/* 0  */
        			EDMA_OPT_DUM_INC,		/* 01 */
        			EDMA_OPT_TCINT_YES,		/* 1  */
        			EDMA_OPT_TCC_OF(15),	        /* 15 */
        			EDMA_OPT_LINK_NO,		/* 0  */
        			EDMA_OPT_FS_NO			/* 0  */
      			),
       		#endif
      		
      		/* SRC Setup */
      		EDMA_SRC_RMK(MCBSP_getRcvAddr(hMcbsp1)),
      		
      		/* CNT Setup */
      		EDMA_CNT_RMK(0, (BUFFER_SIZE * 11)),
      		
      		/* DST Setup */
      		EDMA_DST_RMK((Uint32) recvbuf),        /*recvbuf address*/
      		
      		/* IDX Setup */
      		EDMA_IDX_RMK(0,0),
      		
      		/* RLD Setup */
      		EDMA_RLD_RMK(0,0)
    	);
    		    
    } /* End of ConfigEDMA() */
    
    #endif
    
    
    /*******************************************************************/
    /* void ConfigDMA(void): set up DMA channels 1 & 2 for UART Xmit   */
    /*******************************************************************/
    #if (DMA_SUPPORT)
    
    void ConfigDMA(void)
    {
     
    	DMA_configArgs(hDma1,
                 
    		/* PRICTL Setup */
    		DMA_PRICTL_RMK(
    			DMA_PRICTL_DSTRLD_NONE,
    			DMA_PRICTL_SRCRLD_NONE,
    			DMA_PRICTL_EMOD_HALT,
    			DMA_PRICTL_FS_DISABLE,
    			DMA_PRICTL_TCINT_ENABLE,
    			DMA_PRICTL_PRI_DMA,
    			DMA_PRICTL_WSYNC_XEVT1,
    			DMA_PRICTL_RSYNC_NONE,
    			DMA_PRICTL_INDEX_NA,
    			DMA_PRICTL_CNTRLD_NA,
    			DMA_PRICTL_SPLIT_DISABLE,
    			DMA_PRICTL_ESIZE_16BIT,
    			DMA_PRICTL_DSTDIR_NONE,
    			DMA_PRICTL_SRCDIR_INC,
    			DMA_PRICTL_START_STOP
    		), 
    
    		/* SECCTL Setup */
    		DMA_SECCTL_RMK(
    			DMA_SECCTL_WSPOL_ACTIVEHIGH,
    			DMA_SECCTL_RSPOL_ACTIVEHIGH,
    			DMA_SECCTL_FSIG_NORMAL,
    			DMA_SECCTL_DMACEN_FRAMECOND,
    			DMA_SECCTL_WSYNCCLR_NOTHING,	
    			DMA_SECCTL_WSYNCSTAT_CLEAR, 	
    			DMA_SECCTL_RSYNCCLR_NOTHING, 	
    			DMA_SECCTL_RSYNCSTAT_CLEAR,		
    			DMA_SECCTL_WDROPIE_DISABLE,
    			DMA_SECCTL_WDROPCOND_CLEAR, 	
    			DMA_SECCTL_RDROPIE_DISABLE,
    			DMA_SECCTL_RDROPCOND_CLEAR,		
    			DMA_SECCTL_BLOCKIE_ENABLE,		/* BLOCK IE=1: enables DMA channel int */
    			DMA_SECCTL_BLOCKCOND_CLEAR, 
    			DMA_SECCTL_LASTIE_DISABLE,
    			DMA_SECCTL_LASTCOND_CLEAR,		
    			DMA_SECCTL_FRAMEIE_DISABLE,
    			DMA_SECCTL_FRAMECOND_CLEAR,		
    			DMA_SECCTL_SXIE_DISABLE,
    			DMA_SECCTL_SXCOND_CLEAR			
    		),
    
    		/* SRC Setup */
    		DMA_SRC_RMK((Uint32) xmitbuf),				/*xmitbuf*/
    
    		/* DST Setup */
    		DMA_DST_RMK(MCBSP_getXmtAddr(hMcbsp1)),		/*McBSP DXR */
    		
    		/* XFRCNT Setup */
    		DMA_XFRCNT_RMK(
    			DMA_XFRCNT_FRMCNT_OF(1),
    			DMA_XFRCNT_ELECNT_OF(BUFFER_SIZE*11)
    		)
    
    	);         
                
    	DMA_configArgs(hDma2,
    		
    		/* PRICTL Setup */
    		DMA_PRICTL_RMK(
    			DMA_PRICTL_DSTRLD_NONE,
    			DMA_PRICTL_SRCRLD_NONE,
    			DMA_PRICTL_EMOD_HALT,
    			DMA_PRICTL_FS_DISABLE,
    			DMA_PRICTL_TCINT_ENABLE,
    			DMA_PRICTL_PRI_DMA,
    			DMA_PRICTL_WSYNC_NONE,
    			DMA_PRICTL_RSYNC_REVT1,
    			DMA_PRICTL_INDEX_NA,
    			DMA_PRICTL_CNTRLD_NA,
    			DMA_PRICTL_SPLIT_DISABLE,
    			DMA_PRICTL_ESIZE_16BIT,
    			DMA_PRICTL_DSTDIR_INC,
    			DMA_PRICTL_SRCDIR_NONE,
    			DMA_PRICTL_START_STOP
    		),  
    
    		/* SECCTL Setup */
    		DMA_SECCTL_RMK(
    			DMA_SECCTL_WSPOL_ACTIVEHIGH,
    			DMA_SECCTL_RSPOL_ACTIVEHIGH,
    			DMA_SECCTL_FSIG_NORMAL,
    			DMA_SECCTL_DMACEN_FRAMECOND,
    			DMA_SECCTL_WSYNCCLR_NOTHING,	
    			DMA_SECCTL_WSYNCSTAT_CLEAR, 	
    			DMA_SECCTL_RSYNCCLR_NOTHING, 	
    			DMA_SECCTL_RSYNCSTAT_CLEAR,		
    			DMA_SECCTL_WDROPIE_DISABLE,
    			DMA_SECCTL_WDROPCOND_CLEAR, 	
    			DMA_SECCTL_RDROPIE_DISABLE,
    			DMA_SECCTL_RDROPCOND_CLEAR,		
    			DMA_SECCTL_BLOCKIE_ENABLE,		/* BLOCK IE=1: enables DMA channel int */
    			DMA_SECCTL_BLOCKCOND_CLEAR, 
    			DMA_SECCTL_LASTIE_DISABLE,
    			DMA_SECCTL_LASTCOND_CLEAR,		
    			DMA_SECCTL_FRAMEIE_DISABLE,
    			DMA_SECCTL_FRAMECOND_CLEAR,		
    			DMA_SECCTL_SXIE_DISABLE,
    			DMA_SECCTL_SXCOND_CLEAR			
    		),                                        
                                 
    		/* SRC Setup */
            DMA_SRC_RMK(MCBSP_getRcvAddr(hMcbsp1)),		/*McBSP DRR */
    		
    		/* DST Setup */
    		DMA_DST_RMK((Uint32) recvbuf),              /*recvbuf*/
    
    		/* XFRCNT Setup */
    		DMA_XFRCNT_RMK(
    			DMA_XFRCNT_FRMCNT_OF(1),
    			DMA_XFRCNT_ELECNT_OF(BUFFER_SIZE*11)
    		)
            
    	);         
                
    } /* End of ConfigDMA() */
    
    #endif
      		
    /*******************************************************************/
    /* void ConfigMcBSP(void): Setup for McBSP Configuration           */
    /*******************************************************************/
    void ConfigMcBSP(void)
    {
    
    	MCBSP_Config mcbspCfg1 = {
    		
    		/* SPCR Setup */
    		#if (DMA_SUPPORT)
    			MCBSP_SPCR_RMK(		
    				MCBSP_SPCR_FRST_DEFAULT,		/* 0  */
    				MCBSP_SPCR_GRST_DEFAULT,		/* 0  */
    				MCBSP_SPCR_XINTM_XRDY,			/* 00 */
    				MCBSP_SPCR_XSYNCERR_DEFAULT,	        /* 0  */
    				MCBSP_SPCR_XRST_DEFAULT,		/* 0  */
    				MCBSP_SPCR_DLB_OFF,			/* 0  */
    				MCBSP_SPCR_RJUST_RZF,			/* 00 */
    				MCBSP_SPCR_CLKSTP_DISABLE,		/* 0x */
    				MCBSP_SPCR_RINTM_RRDY,			/* 00 */
    				MCBSP_SPCR_RSYNCERR_DEFAULT,	        /* 0  */
    				MCBSP_SPCR_RRST_DEFAULT			/* 0  */
    			),
    		#endif
    		#if (EDMA_SUPPORT)
    			MCBSP_SPCR_RMK(	
    				MCBSP_SPCR_FREE_YES,			/* 1  */
    				MCBSP_SPCR_SOFT_DEFAULT,		/* 0  */	
    				MCBSP_SPCR_FRST_DEFAULT,		/* 0  */
    				MCBSP_SPCR_GRST_DEFAULT,		/* 0  */
    				MCBSP_SPCR_XINTM_XRDY,			/* 00 */
    				MCBSP_SPCR_XSYNCERR_DEFAULT,	        /* 0  */
    				MCBSP_SPCR_XRST_DEFAULT,		/* 0  */
    				MCBSP_SPCR_DLB_OFF,			/* 0  */
    				MCBSP_SPCR_RJUST_RZF,			/* 00 */
    				MCBSP_SPCR_CLKSTP_DISABLE,		/* 0  */
    				MCBSP_SPCR_DXENA_OFF,			/* 0  */
    				MCBSP_SPCR_RINTM_RRDY,			/* 00 */
    				MCBSP_SPCR_RSYNCERR_DEFAULT,	        /* 0  */
    				MCBSP_SPCR_RRST_DEFAULT			/* 0  */
    			),
    		#endif
    		
    		/* RCR Setup */	
    		#if (DMA_SUPPORT)
    			MCBSP_RCR_RMK(
      		  	MCBSP_RCR_RPHASE_DUAL,			/* 1     */
     		   	MCBSP_RCR_RFRLEN2_OF(1),		/* 00010 */
        			MCBSP_RCR_RWDLEN2_8BIT,			/* 000	 */
        			MCBSP_RCR_RCOMPAND_MSB,			/* 00	 */
        			MCBSP_RCR_RFIG_YES,			/* 1	 */
        			MCBSP_RCR_RDATDLY_1BIT,			/* 01	 */
        			MCBSP_RCR_RFRLEN1_OF(8),		/* 01000 */
        			MCBSP_RCR_RWDLEN1_16BIT			/* 010	 */
        		),
      		#endif
    		#if (EDMA_SUPPORT)
    			MCBSP_RCR_RMK(
      		  	MCBSP_RCR_RPHASE_DUAL,			/* 1     */
     		   	MCBSP_RCR_RFRLEN2_OF(1),		/* 00010 */
        			MCBSP_RCR_RWDLEN2_8BIT,			/* 000	 */
        			MCBSP_RCR_RCOMPAND_MSB,			/* 00	 */
        			MCBSP_RCR_RFIG_YES,			/* 1	 */
        			MCBSP_RCR_RDATDLY_1BIT,			/* 01	 */
        			MCBSP_RCR_RFRLEN1_OF(8),		/* 01000 */
        			MCBSP_RCR_RWDLEN1_16BIT,		/* 010	 */
        			MCBSP_RCR_RWDREVRS_DISABLE 		/* 0     */	
        		),
      		#endif
      	
      		/* XCR Setup */
      		#if (DMA_SUPPORT)
      			MCBSP_XCR_RMK(
                	MCBSP_XCR_XPHASE_DUAL,			/* 1     */
                	MCBSP_XCR_XFRLEN2_OF(1),		/* 00010 */	
        		MCBSP_XCR_XWDLEN2_8BIT,			/* 000	 */
        		MCBSP_XCR_XCOMPAND_MSB,			/* 00	 */
        		MCBSP_XCR_XFIG_YES,			/* 1	 */
        		MCBSP_XCR_XDATDLY_0BIT,			/* 00	 */
        		MCBSP_XCR_XFRLEN1_OF(8),		/* 01000 */
        		MCBSP_XCR_XWDLEN1_16BIT			/* 010	 */
    			),
    		#endif
      		#if (EDMA_SUPPORT)
      			MCBSP_XCR_RMK(
                	MCBSP_XCR_XPHASE_DUAL,			/* 1     */
                	MCBSP_XCR_XFRLEN2_OF(1),		/* 00010 */	
        		MCBSP_XCR_XWDLEN2_8BIT,			/* 000	 */
        		MCBSP_XCR_XCOMPAND_MSB,			/* 00	 */
        		MCBSP_XCR_XFIG_YES,			/* 1	 */
        		MCBSP_XCR_XDATDLY_0BIT,			/* 00	 */
        		MCBSP_XCR_XFRLEN1_OF(8),		/* 01000 */
        		MCBSP_XCR_XWDLEN1_16BIT,		/* 010	 */
    		MCBSP_XCR_XWDREVRS_DISABLE		/* 0	 */
    			),
    		#endif
    				
    		/* SRGR Setup */    
    		MCBSP_SRGR_RMK(
        		MCBSP_SRGR_GSYNC_FREE,				/* 0	  */
        		MCBSP_SRGR_CLKSP_RISING,			/* 0	  */		
        		MCBSP_SRGR_CLKSM_INTERNAL,			/* 1	  */
        		MCBSP_SRGR_FSGM_DXR2XSR,			/* 0 	  */
        		MCBSP_SRGR_FPER_DEFAULT,			/* 0	  */
        		MCBSP_SRGR_FWID_DEFAULT,			/* 0	  */
     //   	 	MCBSP_SRGR_CLKGDV_OF(40)			/* CLKGDV */
        	 	MCBSP_SRGR_CLKGDV_OF(108)			/* CLKGDV */    	 	
      		),
    		
    		/* MCR Setup */
      		MCBSP_MCR_DEFAULT,  					/* default values */
    
    		/* RCER Setup */
    		#if (C64_SUPPORT)
    			MCBSP_RCERE0_DEFAULT,
    			MCBSP_RCERE1_DEFAULT,
    			MCBSP_RCERE2_DEFAULT,
    			MCBSP_RCERE3_DEFAULT, 
    		#else	
      			MCBSP_RCER_DEFAULT, 					/* default values */
    		#endif
    		
    		/* XCER Setup */
    		#if (C64_SUPPORT)
    			MCBSP_XCERE0_DEFAULT,
    			MCBSP_XCERE1_DEFAULT,
    			MCBSP_XCERE2_DEFAULT,
    			MCBSP_XCERE3_DEFAULT, 
    		#else
      			MCBSP_XCER_DEFAULT, 					/* default values */
    		#endif
    		
    		/* PCR Setup */
      		MCBSP_PCR_RMK(
        		MCBSP_PCR_XIOEN_SP,				/* 0 */
        		MCBSP_PCR_RIOEN_SP,				/* 0 */
        		MCBSP_PCR_FSXM_INTERNAL,			/* 1 */
        		MCBSP_PCR_FSRM_EXTERNAL,			/* 0 */
        		MCBSP_PCR_CLKXM_OUTPUT,				/* 1 */
        		MCBSP_PCR_CLKRM_OUTPUT,				/* 1 */
        		MCBSP_PCR_CLKSSTAT_0,				/* 0 */
        		MCBSP_PCR_DXSTAT_0,				/* 0 */
        		MCBSP_PCR_FSXP_ACTIVELOW,			/* 1 */
        		MCBSP_PCR_FSRP_ACTIVELOW,			/* 1 */
        		MCBSP_PCR_CLKXP_RISING,				/* 0 */
    		MCBSP_PCR_CLKRP_FALLING				/* 0 */
        	)
    	};
    	
    	MCBSP_config(hMcbsp1, &mcbspCfg1);
    	
    }	/* end of Config_McBSP(void) */
    
    
    
    /*******************************************************************/
    /* void ProcessTransmitData(void)                                  */
    /*                                                                 */
    /* This function expands each of the 8-bit ASCII characters in the */
    /* transmit string "xmit_msg" into UART transmission 16-bit word   */
    /* and place them in the transmit buffer "xmitbuf".  In addition,  */
    /* 16-bit Start and 8-bit Stop framing words, respectively, are    */
    /* inserted before and after each of the ASCII characters in the   */
    /* buffer.                                                         */
    /*******************************************************************/
    void ProcessTransmitData(void)
    {
    	int		i;
    	short	cnt = 1;
    	unsigned char 	xmit_char;
    	unsigned short	*xmitbufptr;
    	
    	/* point to Transmit Buffer	*/
    	xmitbufptr = (unsigned short *)xmitbuf;
    
    	for (i=0; i<(sizeof(xmitbuf)/sizeof(unsigned int)); i++)
    	{
    		xmitbufptr[i] = 0x0000;	/* zero fill buffer	*/
    	}
    
    	xmitbufptr = (unsigned short *)xmitbuf;	
    	
    	/* Process data BYTES in xmit_msg[] and put in xmit buffer	*/
    	for (i = 0; i < BUFFER_SIZE; i++)
    	{     
    	    /*Get transmit character (one byte) from xmit_msg[] and put in xmit buffer*/
    		xmit_char	=	xmit_msg[i];
    	
    		/* Process each BYTE of transmit character	*/
    		for (cnt = -1; cnt < 10; cnt++)
    		{
    			if (cnt == -1)
    				*xmitbufptr++ 	= 	0x0000;
    			
    			else if (cnt == 8 || cnt ==9)
    				*xmitbufptr++ 	= 	0xFFFF;
    			
    			else if (xmit_char & (1 << cnt))
    				*xmitbufptr++	=	0xFFFF;
    			
    			else
    				*xmitbufptr++	=	0x0000;
    								
    		}	/* end for cnt	*/	      
    		
    	}	/* end for i	*/
    	
    }	/* end ProcessTransmitData	*/
    
    
    /*******************************************************************/
    /* void ProcessReceiveData(void)                                   */
    /*                                                                 */
    /* This function decodes the data in the receive buffer, "recvbuf" */
    /* and strips the framing start (0x0000) and Stop (0xFFFF) words.  */
    /* It calls the subroutine VoteLogic() to determine each bit of    */
    /* the ASCII character.  It then puts the result in recv_msg.      */
    /*******************************************************************/
    void ProcessReceiveData(void)
    {
    	int	i;
    	unsigned char recv_char = 0;
    	short cnt = -1;
    	short recv_val;
    	unsigned short	raw_data;
    	unsigned short	*recvbufptr;    /*receive buffer pointer*/
    
    	/* Point to the receive buffer	*/
    	recvbufptr	= (unsigned short *)recvbuf;
    
    	/* Process all data in the Receive buffer	*/
    	for (i = 0; i < BUFFER_SIZE; i++)
    	{
    		recv_char = 0;
    		
    		/* Process each UART frame	*/
    		for (cnt = -1; cnt < 10; cnt++)
    		{
    			if(cnt == -1 || cnt == 8 || cnt == 9)
    			{
    				/* Ignore Start and Stop bits	*/
    				*recvbufptr++;
    			}
    			else
    			{
    				/* Get 16-bit data from receive buffer	*/
    				raw_data	=	*recvbufptr;
    				recvbufptr++;
    				
    				/* get the value of the majority of the bits	*/
    				recv_val	=	VoteLogic(raw_data);
    				
    				/* put received bit into proper place	*/
    				recv_char	+= recv_val << cnt;
    			}	
    		}	/* end for cnt	*/
    	
    		/* A full BYTE is decoded. Put in result: recv_msg[i]	*/
    		recv_msg[i]	=	recv_char;
    
    	}	/* end for i	*/
    	
    }	/* end ProcessReceiveData() function	*/
    
    
    /*******************************************************************/
    /* void CheckTestCase(void)                                        */
    /*******************************************************************/
    int CheckTestCase(void)
    {
    	unsigned short *source;
    	unsigned short *result;
    	unsigned int i = 0;
    	short cnt = -1;
    	int error = 0;
    	
    	source = (unsigned short *) xmitbuf;
    	result = (unsigned short *) recvbuf;
    	
    	for (i = 0; i < BUFFER_SIZE ; i++)
    	{
    		for (cnt = -1; cnt < 10; cnt++)
    		{
    			/* Ignore the start and stop bits */
    			if(cnt == -1 || cnt == 8 || cnt ==9)
    			{
    				source++;
    				result++;
    			}
    			else
    			{
    				if (*source != *result)
    				{
    					error = i + 1;
    					break;
    				}
    				source++;
    				result++;
    			}
    		}
    	}
    	
    	return(error);
    	
    }	/* end CheckTestCase() function */
    
    
    /*******************************************************************/
    /* short VoteLogic(unsigned short)                                 */
    /*                                                                 */
    /* This function decoded the received character by testing the     */
    /* center 4 bits of the baud.  A majority rule is used for the     */
    /* decoding.                                                       */
    /*******************************************************************/
    short VoteLogic(unsigned short value)
    {
    	short returnvalue;
    
    	switch	((value	>>	6)	& 0x0F)
    	{
    		case	0:
    		case	1:			
    		case	2:	
    		case	3:				
    		case	4:	
    		case	5:	
    		case	6:	
    		case	8:	
    		case	9:												
    		case	10:
    						returnvalue = 0;
    						break;	
    		case	7:	
    		case	11:							
    		case	12:	
    		case	13:	
    		case	14:							
            case	15:
            				returnvalue = 1 ;
            				break;
    	}	/* end switch	*/ 
    	
    	return (returnvalue);
    
    }	/* end VoteLogic() funciton	*/     
    
    
    /*******************************************************************/
    /* EDMA Data Transfer Completion ISRs                              */
    /*******************************************************************/
    
      
    interrupt void c_int11(void)  /* DMA 2 */
    {
    	#if (DMA_SUPPORT)
    		transmit_done = TRUE;
    		printf("Transmit Completed\n");
    	#endif
    }
    
    interrupt void c_int09(void)  /* DMA 1 */
    {
    	#if (DMA_SUPPORT)
    		receive_done = TRUE;
    		printf("Receive Completed\n");
    	#endif
    }
    
    
    interrupt void c_int08(void)
    {
    	#if (EDMA_SUPPORT)
    		if (EDMA_intTest(14))
    		{
    			EDMA_intClear(14);
    			transmit_done = TRUE;
    			printf("Transmit Completed\n");
    		}
    	
    		if (EDMA_intTest(15))
    		{
    			EDMA_intClear(15);
    			receive_done = TRUE;
    			printf("Receive Completed\n\n");
    		}
    	#endif
    }
    

    /*  ===========================================================================
     *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
     *
     *   Use of this software is controlled by the terms and conditions found in 
     *   the license agreement under which this software has been supplied.
     *   ==========================================================================
     */
    
    /** ===========================================================================
     *
     *   @file  Mcbsp_Edma_example.c
     *
     *   @path  $(CSLPATH)\example\mcbsp\mcbsp_edma\src
     *
     *   @desc  Example of MCBSP
     *
     *  ============================================================================
     *   @n Target Platform: EVM
     *  ============================================================================
     *   @n <b> Example Description </b>
     *   @n In this example, the MCBSP0 is configured in digital loopback mode,
     *      with 32 bit data transfer, using sample rate generator to synchronize 
     *      the frames.Edma mode of transmission is selected.
     *      This example,
     *          1. Initializes and opens mcbsp module. 
     *          2. Sets up the hardware to default values and multi channel 
     *             32 bit data transfer i.e., CSL_mcbspHwSetup() is called for 
     *             module configuration.
                3. Sets up interrupts corresponding to EDMA and MCBSP.
     *          4. Sets up EDMA for synchronizing ate MCBSP.
     *          5. Enables MCBSP to Transmit/Receive Data.
     *          7. Waits for the interrupt and once the transfer is done closes 
     *             the EDMA.  
     *          8. Does the data comparison to ensure the validity of the data.
     *          9. Displays the messages based on step 8.
     *
     * =============================================================================
     *      
     *   <b> Procedure to run the example </b>
     *   @verbatim
     *      1. Configure the CCS setup to work with the emulator being used
     *      2. Please refer CCS manual for setup configuration and loading 
     *         proper GEL file
     *      3. Launch CCS window
     *      4. Open project Mcbsp_Edma_example.pjt
     *      5. Build the project and load the .out file of the project.
     *          
     *   @endverbatim
     *
     */
     
    
    /* =============================================================================
     *  Revision History
     *  ===============
     *  9-Aug-2006 RR File Created.
     *
     * =============================================================================
     */
    
    #include <edmaCommon.h>
    #include <cslr_dev.h>
    
    /* Define data count */
    #define DATATX_COUNT                64
    
    /* Global for mcbsp */
    Uint8               srcBuff[DATATX_COUNT];
    Uint8               dstBuff[DATATX_COUNT];
    volatile Uint32     intFlag = 0;
    volatile Uint32     rxintFlag = 0;  
    
    /* Handle for the MCBSP instance used in test */
    CSL_McbspHandle   hMcbsp;
    
    /* Macro that gives 2 CLK delay cycles */
    #define WAIT_FOR_1_CLK  do {                                   \
                                volatile int delayCnt = 1;      \
                                while(delayCnt > 0) --delayCnt; \
                               }while (0)             
    
    /* Global data definition */
    CSL_McbspGlobalSetup mcbspGbl = {
        CSL_MCBSP_IOMODE_TXDIS_RXDIS ,
        CSL_MCBSP_DLBMODE_ON,
        CSL_MCBSP_CLKSTP_DISABLE
    };
    
    /** Receive Data Setup defaults */
    CSL_McbspDataSetup mcbspRxData = {
        CSL_MCBSP_PHASE_SINGLE,
        CSL_MCBSP_WORDLEN_32,
         1,            //frame length
        (CSL_McbspWordLen)0,
         0,
        CSL_MCBSP_FRMSYNC_IGNORE, //frame sinc ignore
        CSL_MCBSP_COMPAND_OFF_MSB_FIRST,
        CSL_MCBSP_DATADELAY_0_BIT,
        CSL_MCBSP_RJUSTDXENA_RJUST_RZF , 
        CSL_MCBSP_INTMODE_ON_READY,   
        CSL_MCBSP_32BIT_REVERS_DISABLE
    };
    /** Transmit Data Setup defaults */
    CSL_McbspDataSetup mcbspTxData = {
        CSL_MCBSP_PHASE_SINGLE,
        CSL_MCBSP_WORDLEN_32,
         1,
        (CSL_McbspWordLen)0,
         0,
        CSL_MCBSP_FRMSYNC_IGNORE,
        CSL_MCBSP_COMPAND_OFF_MSB_FIRST,
        CSL_MCBSP_DATADELAY_0_BIT,
        CSL_MCBSP_RJUSTDXENA_DXENA_OFF , 
        CSL_MCBSP_INTMODE_ON_READY,   
        CSL_MCBSP_32BIT_REVERS_DISABLE
    };
    
    /** Clock Setup defaults */
    CSL_McbspClkSetup mcbspClock = {
        CSL_MCBSP_FSCLKMODE_INTERNAL,    /* XMT Frame-sync */
        CSL_MCBSP_FSCLKMODE_INTERNAL,    /* RCV Frame-sync */
        CSL_MCBSP_TXRXCLKMODE_INTERNAL,  /* XMT clock */
        CSL_MCBSP_TXRXCLKMODE_INTERNAL,  /* RCV clock */
        CSL_MCBSP_FSPOL_ACTIVE_HIGH,     /* XMT Frame-sync Active High */
        CSL_MCBSP_FSPOL_ACTIVE_HIGH,     /* RCV Frame-sync Active High */
        CSL_MCBSP_CLKPOL_TX_RISING_EDGE, /* XMT clock Rising Edge */
        CSL_MCBSP_CLKPOL_RX_FALLING_EDGE,/* RCV clock Falling Edge */
        1,                               /* Frame-sync pulse width = 1 bit */
        0x40,                            /* Frame-sync pulse period  */
        0x1,                             /*clk divide by 2 */
        CSL_MCBSP_SRGCLK_CLKCPU,
        CSL_MCBSP_CLKPOL_TX_RISING_EDGE ,/* CLKS pin signal Rising Edge */
        CSL_MCBSP_TXFSMODE_DXRCOPY,
        CSL_MCBSP_CLKGSYNCMODE_OFF  /* GSYNC = 0 means no clock synchronisation */
    };
    
    CSL_McbspMulChSetup mcbspMul = {
        CSL_MCBSP_PARTMODE_2PARTITION, /* RX */
        CSL_MCBSP_PARTMODE_2PARTITION, /* TX */
        (Uint16)0,        /*  rxMulChSel */
        (Uint16)0,        /*  txMulChSel */
        CSL_MCBSP_PABLK_0,/* rxPartABlk */
        CSL_MCBSP_PBBLK_1,/* rxPartBBlk */
        CSL_MCBSP_PABLK_0,/* txPartABlk */
        CSL_MCBSP_PBBLK_1 /* txPartABlk */
    };
    
    CSL_McbspHwSetup myHwSetup = {
        &mcbspGbl,
        &mcbspRxData,
        &mcbspTxData,
        &mcbspClock,
        &mcbspMul,
        CSL_MCBSP_EMU_FREERUN,
        NULL
    };
    
    /* Global Edma Tcc handler table */
    CSL_IntcEventHandlerRecord      EventHandler[30];
    CSL_IntcContext                 intcContext; 
    CSL_IntcGlobalEnableState       state;
    CSL_Status                      intStat,status;
    CSL_IntcEventHandlerRecord      EventRecord;
    CSL_IntcEventHandlerRecord      EventRecord1; 
    CSL_IntcEventHandlerRecord      record[2];
    CSL_IntcObj                     intcObjEdma,intcObjEdma1;
    CSL_IntcHandle                  hIntcEdma,hIntcEdma1; 
    CSL_IntcParam                   vectId,vectId1;
    
    CSL_Edma3Handle          hModule;
    CSL_Edma3ChannelHandle   hChannel;
    CSL_Edma3ChannelHandle   hChannel1;
    CSL_Edma3ChannelErr      chErrClear;
        
    /* function prototype */
    void setupInterrupts(void);
    void txmyIsr();
    void rxmyIsr();
    void mcbsp_edma_example(void);
    void mcbsp_edma_setup(void);
    
    /*
     * =============================================================================
     *   @func   main
     *
     *   @desc
     *     This is the main routine,which invokes the test scripts
     * =============================================================================
     */
    void main (
        void    
    )
    {
        Bool  mcbsp0En;
        
        /* Enable Mcbsp0 */
        /* Unlock the PERCFG0 register */
        CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, 
                   UNLOCK);
                   
        /* Enable the powersaver for the MCBSP 0 */
        CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_MCBSP0CTL, 
                   ENABLE);
        
        do {
            mcbsp0En = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0, 
                                       DEV_PERSTAT0_MCBSP0STAT);
        } while (mcbsp0En != TRUE);
    
        printf("Powersaver for MCBSP 0 is enabled\n");
    
        /* Invoke the example */
        mcbsp_edma_example ();
        
        printf("===============================================================\n");
        
        return;
    }
    
     /*
     * ============================================================================
     * @func  mcbsp_edma_example
     *
     * @desc
     *     This function performs following steps:
     *      -#  Opens one MCBSP port
     *      -#  Resets MCBSP XMT, RCV and Enable SRGR, Frame-sync
     *      -#  Sets up MCBSP with the initialized hwSetup function
     *          and waits for 1 CLK cycles
     *      -#  After all the data is transmitted out of MCBSP, it compares 
     *          the two buffers and prints the result to stdout
     *      -#  In the end it closes the MCBSP instance that was opened
     *
     * ============================================================================
     */
    void mcbsp_edma_example (void)
    {
        CSL_Status        status = CSL_SOK;
        CSL_McbspContext  pContext;
        CSL_McbspObj      mcbspObj;
        Uint16            i;
        Uint16            success = 1;
        CSL_BitMask16     ctrlMask;
        
        /* Data Arrays */   
        for (i = 0;i < DATATX_COUNT; i++) {
          srcBuff[i] = i;
          dstBuff[i] = 0;
       }
    
        /* Initialize the MCBSP CSL module */
        status = CSL_mcbspInit(&pContext);
        
        /* Open the CSL module */
        hMcbsp = CSL_mcbspOpen (&mcbspObj, CSL_MCBSP_0, NULL, &status);
           
        /* Setup hardware parameters */
        status= CSL_mcbspHwSetup (hMcbsp , &myHwSetup);
    
        /* Disable MCBSP transmit and receive */
        ctrlMask =   CSL_MCBSP_CTRL_SRG_ENABLE
                   | CSL_MCBSP_CTRL_FSYNC_ENABLE
                   | CSL_MCBSP_CTRL_TX_DISABLE
                   | CSL_MCBSP_CTRL_RX_DISABLE;
        status = CSL_mcbspHwControl(hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, &ctrlMask);
            
    	WAIT_FOR_1_CLK; 
     
        /* setup Edma for Mcbsp */   
        mcbsp_edma_setup ();
    
    	/* All done now, close the port. */
        CSL_mcbspClose(hMcbsp);
        
        /* Check data to make sure transfer was successful */
        for (i = 0; i < DATATX_COUNT; i++) {
            if (srcBuff[i] != dstBuff[i]) {
                success = 0;
                break;
            }
        }
        
        for (i = 0; i < DATATX_COUNT; i++) {
            if (success == 1) 
                printf("RxData = %d\t txData=%d\n", dstBuff[i],srcBuff[i]);
            else {
                printf("RxData = %d\t txData=%d\n", dstBuff[i],srcBuff[i]);
                return;
            }
        }
        
        printf("\n%s",success?"TRANSMISSION SUCCESS\n":"TRANSMISSION: EXAMPLE FAILED\n");         
    
        return;
    }
    
    /**
     *  ============================================================================
     *  @n@b    mcbsp_edma_setup
     *
     * @desc
     *     This function performs follwing steps:
     *      -#  Set up interrupts corresponding to EDMA and MCBSP
     *      -#  Set up EDMA for synchronising with MCBSP
     *      -#  Enable MCBSP to Trax Data.
     *      -#  Wait for the interrupt and once the transfer is done close the EDMA 
     * ============================================================================
     */
    
    void mcbsp_edma_setup (
        void
    )
    {   
        
        CSL_Edma3ParamHandle     hParamBasic;
        CSL_Edma3ParamHandle     hParamBasic1;
        CSL_Edma3ParamSetup      myParamSetup;
        CSL_Edma3ParamSetup      myParamSetup1;
        CSL_Edma3ChannelObj      ChObj,ChObj1;
        CSL_Edma3ChannelAttr     chParam;
        CSL_Edma3Context         edmaContext;
        CSL_Edma3Obj             edmaObj;    
        CSL_Edma3QueryInfo       info;
        CSL_Edma3CmdIntr         regionIntr; 
        CSL_Edma3CmdDrae         regionAccess;
        Uint32                   i, j; 
        CSL_BitMask16            ctrlMask;
      
        for (i = 0, j = 1; i < DATATX_COUNT;i++,j++) {
            srcBuff[i] = j;
            dstBuff[i] = 0;
        }   
     
        /* Intc Module Initialization */
        intcContext.eventhandlerRecord = EventHandler;
        intcContext.numEvtEntries = 10;
    
        CSL_intcInit(&intcContext);
        
        /* Enable NMIs */
        CSL_intcGlobalNmiEnable();
    
        /* Enable Global Interrupts */
        intStat = CSL_intcGlobalEnable(&state);
        
        /* Opening a handle for the Event edma */
        vectId = CSL_INTC_VECTID_4;
        hIntcEdma = CSL_intcOpen (&intcObjEdma, CSL_INTC_EVENTID_EDMA3CC_INT0, 
                                 &vectId , NULL);
    
       /* Edma Module Initialization */
        CSL_edma3Init(&edmaContext); 
        
        /* Edma Module Level Open */   
        hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
    
        /* Query Module Info */
        CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INFO, &info); 
    
        /********************************Setup for Tx******************************/
    
        /* Setup the DRAE Masks */
        regionAccess.region = CSL_EDMA3_REGION_0;
        regionAccess.drae   = 0xFFFF;      
        regionAccess.draeh  = 0;         
        
        CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE,&regionAccess);
           
        /* Open transmit channel */
        chParam.regionNum = CSL_EDMA3_REGION_0;
        chParam.chaNum = CSL_EDMA3_CHA_XEVT0;
        hChannel = CSL_edma3ChannelOpen(&ChObj,
                            CSL_EDMA3,
                            &chParam,                            
                            &status); 
    
        /* Channel setup */    
        hParamBasic = CSL_edma3GetParamHandle(hChannel,CSL_EDMA3_CHA_XEVT0, &status);
        
        /* param setup */
        myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
                                                 CSL_EDMA3_TCCH_DIS, \
                                                 CSL_EDMA3_ITCINT_DIS, \
                                                 CSL_EDMA3_TCINT_EN,\
                                                 CSL_EDMA3_CHA_XEVT0, \
                                                 CSL_EDMA3_TCC_NORMAL, \
                                                 CSL_EDMA3_FIFOWIDTH_32BIT, \
                                                 CSL_EDMA3_STATIC_DIS, \
                                                 CSL_EDMA3_SYNC_A,\
                                                 CSL_EDMA3_ADDRMODE_INCR,\
                                                 CSL_EDMA3_ADDRMODE_INCR \
                                                );           
        myParamSetup.srcAddr = (Uint32)srcBuff;
        myParamSetup.dstAddr = (Uint32)CSL_MCBSP_0_TX_EDMA_REGS;
        myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(4,16);       
        myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(4,0);     
        myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,1);     
        myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);     
        myParamSetup.cCnt = 1;          
          
        CSL_edma3HwChannelSetupParam (hChannel, CSL_EDMA3_CHA_XEVT0);
        CSL_edma3HwChannelSetupQue(hChannel, CSL_EDMA3_QUE_1); 
    
        
        
        CSL_edma3ParamSetup(hParamBasic,&myParamSetup); 
        CSL_edma3HwChannelControl(hChannel, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL);    
        
        /********************************Setup for Rx******************************/
        
        /* Open Receive channel */
        chParam.regionNum = CSL_EDMA3_REGION_0;
        chParam.chaNum = CSL_EDMA3_CHA_REVT0;
        hChannel1 = CSL_edma3ChannelOpen(&ChObj1,
                            CSL_EDMA3,
                            &chParam,                            
                            &status);
         
        /* Channel Setup */
        hParamBasic1 = CSL_edma3GetParamHandle(hChannel1,CSL_EDMA3_CHA_REVT0,&status);
        
        /* Param Setup */
        myParamSetup1.option = CSL_EDMA3_OPT_MAKE(FALSE,FALSE,FALSE,TRUE,\
                                                  CSL_EDMA3_CHA_REVT0, \
                                                  CSL_EDMA3_TCC_NORMAL,\
                                                  CSL_EDMA3_FIFOWIDTH_32BIT, \
                                                  CSL_EDMA3_STATIC_DIS, \
                                                  CSL_EDMA3_SYNC_A, \
                                                  CSL_EDMA3_ADDRMODE_INCR, \
                                                  CSL_EDMA3_ADDRMODE_INCR \
                                                 );           
        myParamSetup1.srcAddr = (Uint32)CSL_MCBSP_0_RX_EDMA_REGS;
        myParamSetup1.dstAddr = (Uint32)dstBuff;
        myParamSetup1.aCntbCnt = CSL_EDMA3_CNT_MAKE(4,16);       
        myParamSetup1.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0,4);     
        myParamSetup1.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(
                                                             CSL_EDMA3_LINK_NULL,1);     
        myParamSetup1.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);     
        myParamSetup1.cCnt = 1;          
            
        CSL_edma3HwChannelSetupParam (hChannel1, CSL_EDMA3_CHA_REVT0);
        CSL_edma3HwChannelSetupQue(hChannel1, CSL_EDMA3_QUE_1);
        CSL_edma3ParamSetup(hParamBasic1, &myParamSetup1); 
           
        EventRecord.handler = &eventEdmaHandler;
        EventRecord.arg = (void*)(hModule);
        CSL_intcPlugEventHandler(hIntcEdma,&EventRecord);
    
        /* Enabling event edma  */
        CSL_intcHwControl(hIntcEdma,CSL_INTC_CMD_EVTENABLE,NULL);
    
         /* Hook up the EDMA Event with an ISR */
        EdmaEventHook(CSL_EDMA3_CHA_XEVT0, txmyIsr); 
        EdmaEventHook(CSL_EDMA3_CHA_REVT0, rxmyIsr);  
        
       /* Enable the interrupts */
        regionIntr.region = CSL_EDMA3_REGION_0;
        regionIntr.intr   = 0x3000;      
        regionIntr.intrh  = 0;
        CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr);    
    
        /* Enable the receive channel */
        CSL_edma3HwChannelControl(hChannel1, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL);    
            
        /* Enable MCBSP transmit and receive */
        ctrlMask = CSL_MCBSP_CTRL_TX_ENABLE | CSL_MCBSP_CTRL_RX_ENABLE;
        CSL_mcbspHwControl(hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, &ctrlMask);
        
        WAIT_FOR_1_CLK;
            
        /* wait for Transmit complete Interrupt */
        while (!intFlag);
        
        /* wait for Transmit complete Interrupt */
        while (!rxintFlag);
        
          /* Disable cahnnels and clear the EDMA event registers */
        CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL);
        CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL);
        CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL);
        CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL);
         
        /* clear the error registers */
        chErrClear.missed = TRUE;
        chErrClear.secEvt = TRUE;
        CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEARERR, &chErrClear);
        CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEARERR, &chErrClear);
        
        CSL_edma3ChannelClose(hChannel);
        CSL_edma3ChannelClose(hChannel1);
        CSL_edma3Close(hModule);
        CSL_intcClose (hIntcEdma);
    }
    
    /*
     * ============================================================================
     *   @func   txmyIsr
     *
     *   @desc
     *     This function is the interrupt service routine for transmit data
     *
     *  @arg  
     *      None
     *
     *  @return
     *      None
     * ============================================================================
    */
    
    void txmyIsr()
    {
    
        intFlag = 1;
    }
    
    /*
     * ============================================================================
     *   @func   rxmyIsr
     *
     *   @desc
     *     This function is the interrupt service routine for receive data
     *
     *  @arg  
     *      None
     *
     *  @return
     *      None
     * ============================================================================
    */
    
    void rxmyIsr()
    {
    
        rxintFlag = 1;
    }
    
    


    The sprc234 sample code has been confirmed to operate normally.
    So, using the sprc234 sample code, attempts to create a UART-EDMA3 Interrupt.

    But the McBSP of the sprc234 file modify to UART, UART received data is not read correctly.

    EDMA Channel Parameter settings for the UART seems to be wrong.


    In this regard, please advise.

  • Was resolved by modifying the code below of McBSP_EDMA_example.c content.

        myParamSetup1.dstAddr "= (UInt32) recvbuf,"
        myParamSetup1.aCntbCnt = CSL_EDMA3_CNT_MAKE (2, (BUFFER_SIZE * 11));
        myParamSetup1.srcDstBidx = CSL_EDMA3_BIDX_MAKE (0,2);

    Thank you.

  • Hi Jeong Sang Gi,

    Can you please share the changes needs to be done for the mcbsp_edma_example.c for MCBSP-UART implementation?

    Thanks and Regards,
    Mithun