Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.
How many external interrupts can I configure with the AM3892?
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Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.
How many external interrupts can I configure with the AM3892?
Every GPIO can be used to trigger an interrupt on the host processor. The images were taken taken from the TRM.
DM816x/AM389x TRM: http://www.ti.com/lit/ug/sprugx8b/sprugx8b.pdf
Hi Michael,
Michael Questo said:7 NMI External Pin
I think this NMI is not related to the GPIO module and GPIO interrupt signals.
Michael Questo said:How many external interrupts can I configure with the AM3892?
Michael Questo said:Is there a restriction on which pins may be used?
The TRM and datasheet states we can configure all 64 GPIO pins as external interrupts.
Michael Questo said:Is there some application example of how to configure the external interrupts from GPIO pins?
This is the official TI81xx GPIO driver user guide: http://processors.wiki.ti.com/index.php/TI81XX_PSP_GPIO_Driver_User_Guide, see section 3 IRQ handling
Also you can refer to the below wiki pages, which are for old Davinci devices, but the approach can be reused for DM816x/AM389x :
http://processors.wiki.ti.com/index.php/Configuring_GPIO_Interrupts
http://processors.wiki.ti.com/index.php/Avoiding_Double_Interrupts_with_the_GPIO_Peripheral
BR
Pavel
Michael Questo said:Q1a: I do not see where I can control the assertion of Int#96 vs Int#97. Can you please point me to that register?
Int#96 correspond to GPIOINT0A (GPIO0 interrupt 1). The corresponding GPIO registers are:
GPIO0.GPIO_IRQSTATUS_RAW_0
GPIO0.GPIO_IRQSTATUS_0
GPIO0.GPIO_IRQSTATUS_SET_0
GPIO0.GPIO_IRQSTATUS_CLR_0
Int#97 correspond to GPIOINT0B (GPIO0 interrupt 2). The corresponding GPIO registers are:
GPIO0.GPIO_IRQSTATUS_RAW_1
GPIO0.GPIO_IRQSTATUS_1
GPIO0.GPIO_IRQSTATUS_SET_1
GPIO0.GPIO_IRQSTATUS_CLR_1
For configuring/enabling the interrupts from the Cortex-A8 CPU side, see AM389x TRM, chapter 12 Interrupt Controller
Michael Questo said:Q1b: I assume that these registers indicate the status, Enable/Disable for the interrupt for Bank 0 GPIO’s (from TRM). Do you agree?
I agree.
Michael Questo said:Q2a: I do not see where I can control the assertion of Int#98 vs Int#99. Can you please point me to that register?
Int#98 correspond to GPIOINT1A (GPIO1 interrupt 1). The corresponding GPIO registers are:
GPIO1.GPIO_IRQSTATUS_RAW_0
GPIO1.GPIO_IRQSTATUS_0
GPIO1.GPIO_IRQSTATUS_SET_0
GPIO1.GPIO_IRQSTATUS_CLR_0
Int#99 correspond to GPIOINT1B (GPIO1 interrupt 2). The corresponding GPIO registers are:
GPIO1.GPIO_IRQSTATUS_RAW_1
GPIO1.GPIO_IRQSTATUS_1
GPIO1.GPIO_IRQSTATUS_SET_1
GPIO1.GPIO_IRQSTATUS_CLR_1
For configuring/enabling the interrupts from the Cortex-A8 CPU side, see AM389x TRM, chapter 12 Interrupt Controller
Michael Questo said:Q2b: I assume that these registers indicate the status, Enable/Disable for the interrupt for Bank 1 GPIO’s (from TRM). Do you agree?
I agree.
Michael Questo said:Q3: How do I direct these functions to Bank 0 or 1 of the GPIO? I do not see separate registers for these functions as I would expect!
As these registers are not directly related to the interrupt management in the GPIO, these registers are common for GPIOx Bank 1 and 2.
BR
Pavel
Pavel,
From the response, I see exactly what I would have expected, BUT that is NOT what the TRM (SPRUGX7, 1 July 2011) says!
You indicate the following:
GPIOx.GPIO_IRQSTATUS_RAW_y
GPIOx.GPIO_IRQSTATUS_y
GPIOx.GPIO_IRQSTATUS_SET_y
GPIOx.GPIO_IRQSTATUS_CLR_y
For x = Int0 or Int1
y = 0(IntxA) or 1(IntxB)
The problem is that the TRM does not have the secondary set of GPIO registers (i.e. GPIO1.GPIO_IRQSTATUS_RAW_y …..)!
Unfortunately, you did not reference the offsets specific to this processor in his response.
I see offset space ( 44h-110h) where they could reside. Are they missing in the reference manual?
What are the correct offset addresses for the additional registers?
Here is what is listed in the AM3892 TRM,
0h GPIO_REVISION GPIO Revision Register Section 8.3.1
10h GPIO_SYSCONFIG System Configuration Register Section 8.3.2
20h GPIO_EOI End of Interrupt Register Section 8.3.3
24h GPIO_IRQSTATUS_RAW_0 Status Raw Register for Interrupt 1 Section 8.3.4
28h GPIO_IRQSTATUS_RAW_1 Status Raw Register for Interrupt 2 Section 8.3.4
2Ch GPIO_IRQSTATUS_0 Status Register for Interrupt 1 Section 8.3.5
30h GPIO_IRQSTATUS_1 Status Register for Interrupt 2 Section 8.3.5
34h GPIO_IRQSTATUS_SET_0 Enable Set Register for Interrupt 1 Section 8.3.6
38h GPIO_IRQSTATUS_SET_1 Enable Set Register for Interrupt 2 Section 8.3.6
3Ch GPIO_IRQSTATUS_CLR_0 Enable Clear Register for Interrupt 1 Section 8.3.7
40h GPIO_IRQSTATUS_CLR_1 Enable Clear Register for Interrupt 2 Section 8.3.7
114h GPIO_SYSSTATUS System Status Register Section 8.3.8
130h GPIO_CTRL Module Control Register Section 8.3.9
134h GPIO_OE Output Enable Register Section 8.3.10
138h GPIO_DATAIN Data Input Register Section 8.3.11
13Ch GPIO_DATAOUT Data Output Register Section 8.3.12
140h GPIO_LEVELDETECT0 Low-level Detection Enable Register Section 8.3.13
144h GPIO_LEVELDETECT1 High-level Detection Enable Register Section 8.3.14
148h GPIO_RISINGDETECT Rising-edge Detection Enable Register Section 8.3.15
14Ch GPIO_FALLINGDETECT Falling-edge Detection Enable Register Section 8.3.16
150h GPIO_DEBOUNCENABLE Debounce Enable Register Section 8.3.17
154h GPIO_DEBOUNCINGTIME Debouncing Time Register Section 8.3.18
190h GPIO_CLEARDATAOUT Clear Data Output Register Section 8.3.19
194h GPIO_SETDATAOUT Set Data Output Register Section 8.3.20
=============================================================================================================
To the question about control of individual GPIO’s you responded:
“Q3: How do I direct these functions to Bank 0 or 1 of the GPIO? I do not see separate registers for these functions as I would expect!”
“As these registers are not directly related to the interrupt management in the GPIO, these registers are common for GPIOx Bank 1 and 2.”
The question was referring to the generic control of the GPIO’s. In the part there are 64 GPIOs.
In your response, you referenced the bank 0 and 1 above (e.g. GPIO0.GPIO_IRQSTATUS_RAW_0 vs GPIO1.GPIO_IRQSTATUS_RAW_0). I believe you misunderstood my question.
64 GPIO’s require at least two 32 bit registers to control each of the identified functions. Looking again at the register map above from the TRM, there is additional register space from 158h to 18C. Are the additional registers in this offset area? What are the correct offset addresses of the additional registers?
John,
AM389x TRM list the registers offset, while the base address is listed in the AM389x datasheet.
In AM389x device, we have 2 GPIO controllers, each controlling 32 pins (64 pins total). GPIO0 is at address 0x48032000, GPIO1 is at address 0x4804C000 (see datasheet). Thus we have:
GPIO0.GPIO_IRQSTATUS_RAW_0 - 0x48032024
GPIO0.GPIO_IRQSTATUS_0 - 0x4803202C
GPIO0.GPIO_IRQSTATUS_SET_0 - 0x48032034
GPIO0.GPIO_IRQSTATUS_CLR_0 - 0x4803203C
GPIO0.GPIO_IRQSTATUS_RAW_1 - 0x48032028
GPIO0.GPIO_IRQSTATUS_1 - 0x48032030
GPIO0.GPIO_IRQSTATUS_SET_1 - 0x48032038
GPIO0.GPIO_IRQSTATUS_CLR_1 - 0x48032040
GPIO1.GPIO_IRQSTATUS_RAW_0 - 0x4804C024
GPIO1.GPIO_IRQSTATUS_0 - 0x4804C02C
GPIO1.GPIO_IRQSTATUS_SET_0 - 0x4804C034
GPIO1.GPIO_IRQSTATUS_CLR_0 - 0x4804C03C
GPIO1.GPIO_IRQSTATUS_RAW_1 - 0x4804C028
GPIO1.GPIO_IRQSTATUS_1 - 0x4804C030
GPIO1.GPIO_IRQSTATUS_SET_1 - 0x4804C038
GPIO1.GPIO_IRQSTATUS_CLR_1 - 0x4804C040
No additional registers.
============================================================================================================
We do not have 64 GPIOs, we have 64 GPIO pins which are controlled from only 2 GPIO controllers (GPIO0 and GPIO1).
No additional registers.
First 32 GPIO pins (GP0[0] to GP0[31]) are controlled from GPIO0 registers (0x48032000 + offset). Second 32 GPIO pins (GP1[0] to GP1[31]) are controlled from GPIO1 registers (0x4804C000 + offset).
Let me know if you need more details, and I will try to provide you an example.
BR
Pavel
John,
Are both 32bit registers. Each bit "INTLINE" is mapped to one of the 64 availaable GPIO interrupts.
I'm not sure i fully understand your question. Are you looking for the base address to which you add the offset (e.g. 24h fir GPIO_IRQSTATUS_RAW_0) to in order to look up the value of the IRQStatus (which you would have to mask out of the returned value)?
The base addresses can be found in section 1.5.2.1 L4 Standard Peripheral of the TRM.