Can EDMAs be used to separate in real time the lines of an interlaced image as the image is received without processor core interaction?
A proposed design that I have been asked to examine will be providing what I think can be best described as an interlaced image where odd lines of image data are for 1 group of light frequencies and the even lines of data are for another group of light frequencies. Part of the objective for capturing this data is to separate the odd line data from the even line data into separate buffers in RAM for post capture processing by the DSP. The start of each line (odd and even) will be indicated by an external interrupt (EXT_INT7), and odd lines of data should be transferred to one buffer with incrementing addresses and even lines of data should be transferred to another buffer with incrementing addresses. The source of the data is to be a static FIFO address (part of an FPGA) which can only hold one line's worth of data. Each line of data is approximately 800 bytes and the total (odd plus even) number of lines will be approximately 600.
The EDMAs seem to have considerable flexibility and the goal that I am seeking seems like something that should be within the capabilities of the EDMAs, but I cannot envision a technique for configuring the EDMAs to accomplish this goal. I have examined "Linking EDMA Transfers" as documented in SPRU234C, but I do not think that method will provide the incrementing destination addresses needed for each odd or even line of data. I have also examined "Chaining EDMA Channels" as documented in SPRU234C, but with the same interrupt being used for synchronization of each line of odd and even data it appears that chaining will not work. (Separate interrupts for the odd and even lines of data are not available without redesigning a circuit board and cramming additional functionality into the FPGA.)
Ideas and suggestions on how to accomplish this separation of data would be appreciated.
I am new to this forum and to TI DSPs. Any help is appreciated.