Oddities in dMAX that works with McASP on 6726B

Constantine Musatoff

I use both channels of McASP. I use ARX0[0] to receive and ARX0[1] to transmit on McASP0 and ARX1[0], ARX1[1] to transmit and ARX1[2] to receive on McASP1. All in I2S mode. For beginning I tuned McASPs for program poling. After that I made tune McASPs for dMAX servicing. I wrote interrupt for dMAX working check.

#pragma INTERRUPT( dMax )
interrupt void  dMax( void )
{
	static int i[4] = {0,0,0,0};

	MCASP0->PDSET.dword = TESTLED;
	//while( dMAX->DTCR0.dword )
	{
		if( dMAX->DTCR0.TCC0 ) // Send McASP0
		{
			dMAX->DTCR0.TCC0 = 1;
			i[0]++;
		}
		if( dMAX->DTCR0.TCC1 ) // Rec McASP0
		{
			dMAX->DTCR0.TCC1 = 1;
			i[1]++;
			if(i[1] == 44100)
				asm( "       nop 4");
		}
		if( dMAX->DTCR0.TCC2 ) // Send McASP1
		{
			dMAX->DTCR0.TCC2 = 1;
			i[2]++;
		}
		if( dMAX->DTCR0.TCC3 ) // Rec McASP1
		{
			dMAX->DTCR0.TCC3 = 1;
			i[3]++;
		}
	}
	MCASP0->PDCLR.dword = TESTLED;
}

I set breakpoint on receiving 44100 samples (asm( " nop 4");)

If I enable event (in DEER register) only for receiving on McASP1 or for transmitting then count on break is 88199 for i[2] or i[3] as true. If I enable both events the count of transmitting i[2] is very low, for example 17.

Patch from spra203 id applied. Without patch dMAX do not works.

In what direction should I look for error?

void DmaxMcAsp0_init(void)
{
	// 3.2.1 Steps Required to Set Up a General Purpose Transfer
	// 1.
	dMAX->DEHPR.dword |= (1<<dMAXE_McASP0TX) | (1<<dMAXE_McASP0RX); //

	// 2.
	dMAX->DEPR.dword |= (1<<dMAXE_McASP0TX) | (1<<dMAXE_McASP0RX); //
	//dMAX->DEPR.dword &= ~((1<<dMAXE_McASP0TX) | (1<<dMAXE_McASP0RX));

	// 3.
#define McASP0_Trasfer_Entry 0
	HiMAX->Event[dMAXE_McASP0TX].GP.dword =
			PaRAME_ETYPE_GP | 		// General P
			PaRAME_PTEGP(McASP0_Trasfer_Entry) | 		
			PaRAME_ESIZEGP_32 | 	// work with dwords
			PaRAME_CC(0) |      	//15 bit, 8 bit, 8 bit
			PaRAME_RLOAD_YES |  	// Reload addresses
			PaRAME_TCINT_ENABLE | 	// Interrupt after complete
			PaRAME_ATCINT_DISABLE | // No internal interrupts
			PaRAME_TCC(TCC_McASP0T) |  // Transfer complete code DTCR0.TCC_McASP0T
			PaRAME_SYNC_COUNT0 |   	// Work only count0 on one event
			PaRAME_QTSL_1;         	// One element on transfer

	// 4.
	HiMAX->Entry[McASP0_Trasfer_Entry].GPZ.SRC =
			HiMAX->Entry[McASP0_Trasfer_Entry].GPZ.SRC0 = IData_buf;
	HiMAX->Entry[McASP0_Trasfer_Entry].GPZ.SRC1 = &IData_buf[2];
	HiMAX->Entry[McASP0_Trasfer_Entry].GPZ.DST =
			HiMAX->Entry[McASP0_Trasfer_Entry].GPZ.DST0 =
					HiMAX->Entry[McASP0_Trasfer_Entry].GPZ.DST1 = McASP0_DMA;
	HiMAX->Entry[McASP0_Trasfer_Entry].GPZ.REFERENCE.dword =
			HiMAX->Entry[McASP0_Trasfer_Entry].GPZ.ACTIVE.dword = PaRAME_GPZ_COUNT0(1) | PaRAME_GPZ_COUNT1(2) | PaRAME_GPZ_COUNT2(0);
	//HiMAX->Entry[McASP0_Trasfer_Entry].GPZ.INDX[0].dword = HWORD(1) | LWORD(1);
	HiMAX->Entry[McASP0_Trasfer_Entry].GPZ.INDX[1].dword = HWORD(1) | LWORD(1);

	// 3.
#define McASP0_Rec_Entry 1
	HiMAX->Event[dMAXE_McASP0RX].GP.dword =
			PaRAME_ETYPE_GP | 		// General P
			PaRAME_PTEGP(McASP0_Rec_Entry) | 		
			PaRAME_ESIZEGP_32 | 	// work with dwords
			PaRAME_CC(0) |      	//15 bit, 8 bit, 8 bit
			PaRAME_RLOAD_YES |  	// Reload addresses
			PaRAME_TCINT_ENABLE | 	// Interrupt after complete
			PaRAME_ATCINT_DISABLE | // No internal interrupts
			PaRAME_TCC(TCC_McASP0R) |         // Transfer complete code DTCR0.TCC_McASP0R
			PaRAME_SYNC_COUNT0 |   	// Work only count0 on one event
			PaRAME_QTSL_1;         	// One element on transfer

	// 4.
	HiMAX->Entry[McASP0_Rec_Entry].GPZ.SRC =
			HiMAX->Entry[McASP0_Rec_Entry].GPZ.SRC0 =
					HiMAX->Entry[McASP0_Rec_Entry].GPZ.SRC1 = McASP0_DMA;
	HiMAX->Entry[McASP0_Rec_Entry].GPZ.DST =
			HiMAX->Entry[McASP0_Rec_Entry].GPZ.DST0 = OData_buf;
	HiMAX->Entry[McASP0_Rec_Entry].GPZ.DST1 = &OData_buf[2];
	HiMAX->Entry[McASP0_Rec_Entry].GPZ.REFERENCE.dword =
			HiMAX->Entry[McASP0_Rec_Entry].GPZ.ACTIVE.dword = PaRAME_GPZ_COUNT0(1) | PaRAME_GPZ_COUNT1(2) | PaRAME_GPZ_COUNT2(0);
	HiMAX->Entry[McASP0_Rec_Entry].GPZ.INDX[1].dword = HWORD(1) | LWORD(1);
	//HiMAX->Entry[McASP0_Rec_Entry].GPZ.INDX[1].dword = 0;

	// 5.
	dMAX->DEER.dword |=  (1<<dMAXE_McASP0TX) | (1<<dMAXE_McASP0RX); //

}
void DmaxMcAsp1_init(void)
{
	// 3.2.1 Steps Required to Set Up a General Purpose Transfer
	// 1.
	dMAX->DEHPR.dword |= (1<<dMAXE_McASP1TX) | (1<<dMAXE_McASP1RX); //

	// 2.
	dMAX->DEPR.dword |= (1<<dMAXE_McASP1TX) | (1<<dMAXE_McASP1RX); //
	//dMAX->DEPR.dword &= ~((1<<dMAXE_McASP0TX) | (1<<dMAXE_McASP0RX));

	// 3.
#define McASP1_Trasfer_Entry 2
	HiMAX->Event[dMAXE_McASP1TX].GP.dword =
			PaRAME_ETYPE_GP | 		// General P
			PaRAME_PTEGP(McASP1_Trasfer_Entry) | 		
			PaRAME_ESIZEGP_32 | 	// work with dwords
			PaRAME_CC(0) |      	//15 bit, 8 bit, 8 bit
			PaRAME_RLOAD_YES |  	// Reload addresses
			PaRAME_TCINT_ENABLE | 	// Interrupt after complete
			PaRAME_ATCINT_DISABLE | // No internal interrupts
			PaRAME_TCC(TCC_McASP1T) |  // Transfer complete code DTCR0.TCC_McASP0T
			PaRAME_SYNC_COUNT0 |   	// Work only count0 on one event
			PaRAME_QTSL_4;         	// One element on transfer

	// 4.
	HiMAX->Entry[McASP1_Trasfer_Entry].GPZ.SRC =
			HiMAX->Entry[McASP1_Trasfer_Entry].GPZ.SRC0 = D12_buf;
	HiMAX->Entry[McASP1_Trasfer_Entry].GPZ.SRC1 = &D12_buf[4];
	HiMAX->Entry[McASP1_Trasfer_Entry].GPZ.DST =
			HiMAX->Entry[McASP1_Trasfer_Entry].GPZ.DST0 =
					HiMAX->Entry[McASP1_Trasfer_Entry].GPZ.DST1 = McASP1_DMA;
	HiMAX->Entry[McASP1_Trasfer_Entry].GPZ.REFERENCE.dword =
			HiMAX->Entry[McASP1_Trasfer_Entry].GPZ.ACTIVE.dword = PaRAME_GPZ_COUNT0(2) | PaRAME_GPZ_COUNT1(2) | PaRAME_GPZ_COUNT2(0);
	HiMAX->Entry[McASP1_Trasfer_Entry].GPZ.INDX[0].dword = HWORD(1) | LWORD(1);
	HiMAX->Entry[McASP1_Trasfer_Entry].GPZ.INDX[1].dword = HWORD(1) | LWORD(1);

	// 3.
#define McASP1_Rec_Entry 3
	HiMAX->Event[dMAXE_McASP1RX].GP.dword =
			PaRAME_ETYPE_GP | 		// General P
			PaRAME_PTEGP(McASP1_Rec_Entry) | 		
			PaRAME_ESIZEGP_32 | 	// work with dwords
			PaRAME_CC(0) |      	//15 bit, 8 bit, 8 bit
			PaRAME_RLOAD_YES |  	// Reload addresses
			PaRAME_TCINT_ENABLE | 	// Interrupt after complete
			PaRAME_ATCINT_DISABLE | // No internal interrupts
			PaRAME_TCC(TCC_McASP1R) |         // Transfer complete code DTCR0.TCC_McASP0R
			PaRAME_SYNC_COUNT0 |   	// Work only count0 on one event
			PaRAME_QTSL_1;         	// One element on transfer

	// 4.
	HiMAX->Entry[McASP1_Rec_Entry].GPZ.SRC =
			HiMAX->Entry[McASP1_Rec_Entry].GPZ.SRC0 =
					HiMAX->Entry[McASP1_Rec_Entry].GPZ.SRC1 = McASP1_DMA;
	HiMAX->Entry[McASP1_Rec_Entry].GPZ.DST =
			HiMAX->Entry[McASP1_Rec_Entry].GPZ.DST0 = DADC_buf;
	HiMAX->Entry[McASP1_Rec_Entry].GPZ.DST1 = &DADC_buf[2];
	HiMAX->Entry[McASP1_Rec_Entry].GPZ.REFERENCE.dword =
			HiMAX->Entry[McASP1_Rec_Entry].GPZ.ACTIVE.dword = PaRAME_GPZ_COUNT0(1) | PaRAME_GPZ_COUNT1(2) | PaRAME_GPZ_COUNT2(0);
	HiMAX->Entry[McASP1_Rec_Entry].GPZ.INDX[1].dword = HWORD(1) | LWORD(1);
	//HiMAX->Entry[McASP1_Rec_Entry].GPZ.INDX[1].dword = 0;

	// 5.
	dMAX->DEER.dword |= (1<<dMAXE_McASP1RX) | (1<<dMAXE_McASP1TX); //

}

over 11 years ago

0 Sivaraj Kuppuraj over 11 years ago

TI__Mastermind 35645 points

Hi Constantine,

Thanks for your post.

There are multiple directions to look fo error:

1. If you use dMAX FIFO mode, there could be chances of FIFO watermarking conditons or FIFO buffer errors (underflow or overflow error) and there are dedicated interrupts to enable appropriate error flags in the register to check whether the interrupt triggers on appropriate conditions. Please see Section 1.4.1 & 1.4.2 in the c672x dMAX reference guide as below:

http://www.ti.com/lit/ug/spru795d/spru795d.pdf

2. There could be other chances of discontinuity in dMAX transfer completion, if the TCC values are not mapped appropriately to the corresponig McASP Rx. and Tx. channel bits (ParamSets) for ports 0 & 1 else, if dMAX event nos are not mapped correctly to McASP Rx & Tx channels

Please refer the below E2E threads for your reference:

http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/t/121444.aspx

http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/t/119811.aspx

Please also check to trigger any error interrupts from McASP side. Kindly refer Section 3.6 in the C672x McASP reference guide below to handle the errors from McASP side ( framesync error, clock failure error, buffer underrun/overrun error, dMAX error etc)

http://www.ti.com/lit/ug/spru878b/spru878b.pdf

Thanks & regards,

Sivaraj K

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0 Constantine Musatoff over 11 years ago in reply to Sivaraj Kuppuraj

Intellectual 880 points

Thank you, Sivaraj!

I fined error. Frequency of SYSCLOCK1 was too low.

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Oddities in dMAX that works with McASP on 6726B