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AM1802 JTAG Connection Problems

George Ioakimedes
Genius 4950 points
Other Parts Discussed in Thread: AM1808, AM1802, TPS650061

I have another post going but I wanted this one to be specific to JTAG since I'm not having much luck. I have the AM1808 eXperimenter board with the Blackhawk USB100v2 JTAG Controller. I am using CCS5 and have confirmed that the JTAG Controller can connect to the eXperimenter board.

Unfortunately on our custom board I have the wrong footprint to connect the controller directly to the board so I've made an adapter cable. We have remade the adpater cable a few times and have double checked continuity but we always seem to get an error when we "Test Connection" in CCS5.

  • We have the signals coming directly out of the AM1802 and going to our JTAG header.
  • EMU0/EMU1 are pulled high through 10k resistors to 3.3V
  • TRST is pulled low through a 10k resistor
  • We are using the 20e_cTI-20t_ARM Pin Converter board at the end of the JTAG Controller and out adapter cable plugs into this board so EMU0/EMU1 are not connected.
  • RESET on our board is connected to the reset output pin of a TPS650061 and has been confirmed to go high (1.8V) ~25ms after the 3.3V rail comes up (which is the last rail to come up).

Here is a picture of the JTAG connections:

  • We have 3D X-Rayed the AM1802 and confirmed that it is soldered correctly.
  • The BOOT[7:0] pins are configured for [00011110] using 2.2K PU/PD resistors to 3.3V
  • The power rails have been confirmed to come up in the proper sequence
  • The main clock is confirmed to be at 24MHz, 1.2V level
  • I can also see the RTC clock at 32.768kHz
  • When I change the BOOT mode setup to boot from a SD Card I can see the SD clock as well as traffic on the SD data line.

I have never seen any traffic on the UART1 or UART2 Tx/Rx lines.

I have never been able to pass the JTAG Connection Test.

Does anyone have any idea what could be wrong or what else I can check? I thought that the ROM would output something on UART2 even if the board was able to boot, is this true?

I'm at aloss as to why I cannot get the JTAG Connection Test to pass but perhaps this is a clue as to why I don't see any boot messages?

  • 0
    TI__Mastermind 20790 points

    Hi,

    Please read the section "JTAG/Emulation" at this wiki page, this will help you to troubleshoot the issue
    http://processors.wiki.ti.com/index.php/OMAP-L13x_/_C674x_/_AM1x_Schematic_Review_Checklist#JTAG.2FEmulation
    You can find more details for ARM 20-pin Header at the below wiki pages,
    http://processors.wiki.ti.com/index.php/XDS100
    http://processors.wiki.ti.com/index.php/JTAG_Connectors

     

  • 0 in reply to Pubesh
    TI__Guru*** 125430 points

    Your JTAG pinout looks incorrect.  Please reference this page:

    http://processors.wiki.ti.com/index.php/JTAG_Connectors#Pinout

    Your schematic snippet says "TI 20-pin", but that header doesn't match the cTI header.  You also mention the 20 pin cTI to 20-pin ARM adapter, but your header doesn't match the 20-pin ARM header either.  ?

  • 0 in reply to Brad Griffis
    Genius 4950 points

    Yes, you are correct, the pinout of the header is incorrect, as well as the footprint (1.27mm x 1.27mm). Not quite sure what I was thinking during the board layout other than I wasn't planning on really needing to use JTAG and now it's come back to bite me.

    I was making an adapter cable to go from my board to the USB100v2. I was able to finally get JTAG to connect by grounding the TDIS pin on the cTI 20-pin header (which the 20e_cTI-20t_ARM does).

    I've been doing some preliminary tests with JTAG and am getting unexpected results when trying to manually change DDR memory locations (as a quick test to see if the DDR2 is configured properly).

    I noticed in the documents that the JTAG clock signal is recommended to be buffered and mine is not. I could wire up a buffer chip but I'm wondering if that's necessary if I'm running less that 1MHz?

  • 0 in reply to George Ioakimedes
    TI__Guru*** 125430 points

    George Ioakimedes said:
    I've been doing some preliminary tests with JTAG and am getting unexpected results when trying to manually change DDR memory locations (as a quick test to see if the DDR2 is configured properly).

    What type of error are you seeing?  I think it's more likely that the DDR timings have not been configured correctly, i.e. that the DDR controller configuration is the root cause and not anything with the JTAG.

    As a sanity check you could make sure you can read/write from the internal SRAM inside the device.  If you can do that reliably then that confirms whatever other issues you're having with the DDR are confined to the timings and/or layout.

    George Ioakimedes said:
    I noticed in the documents that the JTAG clock signal is recommended to be buffered and mine is not. I could wire up a buffer chip but I'm wondering if that's necessary if I'm running less that 1MHz?

    I think we generally only recommend buffering if the traces are over 5" long.  And for 1MHz operation even that might be conservative...

  • 0 in reply to Brad Griffis
    Genius 4950 points

    Hi Brad:

    Thanks for the sanity check. Between the ribbon cable from the controller board to the adapter and then my jumper wires from the adapter board to my board is ~9" with the ribbon cable being ~5".

    You can see this thread for what I'm seeing now, RE: New AM1802 Custom Board Bring-up

    At the very end you can see that I use the memory viewer and type in new values but when I type in 1 location 2 other locations are changed which is rather odd.

    Your idea to check the internal SRAM is a good one. I'll have to look up that address and see what happens when I poke it. The debug gel scripts can read ll of the information and I have successfully run a UART test but using the NAND, RAM, and SDMMC tests from the AM1808 all fail.

    George

  • 0 in reply to George Ioakimedes
    TI__Guru*** 125430 points

    Here's the official recommendation from Emulation Fundamentals for TI's DSP Solutions (spra439e.pdf):

    • If the processor is six inches or more from the JTAG header, there could be degradation of the signal due to
      loading of the signal path. In this case, you should use buffers to drive the signals and maintain a suitable
      signal quality to ensure proper emulation (Figure 4). It should be noted that proper buffer selection is as
      important as proper signal routing on the target.

    So I think your design is fine, especially for 1 MHz operation!  I had a quick look at the other thread.  Yes, adaptive clocking is needed to connect (reliably) to the ARM core as I found out in this thread a while back.

  • 0 in reply to Brad Griffis
    Genius 4950 points

    Thanks, I really appreciate you looking into this. With so many variables going on it's nice to know at least 1 thing that should work!.

    I did do a quick test and I was able to change the SRAM memory as expected. I was reading through the gel file that was provided to me in that thread and it configures the RAM for mDDR and not DDR2 as I've said that I have. I'm not convinced that the same configuration can be used for both so I'm trying to modify the GEL file but the changes I made cause the GEL to not load so I obviously have something that it doesn't like.

    2 major difference I see from the RAM on the EVM and what's on my board (besides mDDR vs DDR2) are that the EVM has 4 banks, I have 8 banks so I have BA[2;0] and the EVM has BA[1:0]

    So I don't hijack my own thread I'll post this back on the other thread with the changes I made to see if anyone is listening and can see what's wrong.