Hi AM335x champs,
I'm looking to reduce my 25Mhz EMI on my board by using one of Ti's Spread Spectrum Buffers, CDCS502 or CDCS503 for LVCMOS, to apply dithering to the input clock on OSC0.
"Section 6.2.2.2 OSC0 LVCMOS Digital Clock Source" in the Datasheet describes the requirements for an LVCMOS clock but doesn't make an mention of Spread Spectrum capable.
Will the DPLL in the AM335x support this an SS clock input?
Wolfgang,
Thanks that's really useful, i didn't see that post. Although it looks like it only applies to the clock outputs. I was curious if it were possible to use a spread spectrum device on the LVCMOS input for the main input OSC.
After a bit more investigation here's what I found.
In section 3 "Can I Use the CDCS502/503 in My Application?" of the "Spread Spectrum Clocking Using the CDCS502/503" (http://www.ti.com/lit/an/scaa103/scaa103.pdf) appnote it describes the jitter tolerance of a processor is the main limiting factor for whether or not SSC can be used.
The AM335x's peak-to-peak (periodic) jitter spec is 1% of its reference clock for LVCMOS.
Following the math in the CDCS502 app note. If the Crystal frequency is 25 MHz, then UI = 40 ns and therefore the AM335x's max periodic jitter is 0.01 * 40 ns = 0.40 ns = 400 ps. This limit is only within the limits of the CDCS502/503 for 0% SSC.
