DM814x video2_pll refclock limitation?

Daniel70334

TI folks,

We have developed a product based on the DM814x, using:

DM814x PG 3.0
EZSDK 5.05.02.00
EZSDK OMX/HDVPSS Overlay 5.05.02.00
PSP 04.04.00.02
Most of the Arago updates for both linux and u-boot in ti81xx-master after the v2.6.37_TI81XXPSP_04.04.00.02.patch1 tag

I am currently changing the VIDEO2_PLL (i.e., the clock for the HDMI VENC) to be based on 27 MHz rather than 20 MHz. So far, my mods are working (still need to test more output clocks). However, I have a question about a REFCLK ( = source / (N + 1) ) test, in the file:

board-support/linux-2.6.37-psp04.04.00.02/drivers/video/ti81xx/vpss/system.c

In the function called system_getdividers(). There is the following test to ensure that the REFCLK is less than 2.5 MHz:

VPSSDBG("request clk %dHz\n", reqoutclk);
refclk = TI814X_OSC_FREQ / (n + 1);
if (refclk > ((5 * MHZ) >> 1))
return r;

Can you tell me why this test is here? Is it 2.5 MHz for any source clock, or is this related to the specific original 20 MHz DEVOSC?

Thanks,

Dan -

over 11 years ago

0 Matthijs van Duin over 11 years ago

Mastermind 8040 points

Valid range for the refclk (input clock to the multiplier) of an LJ-type PLL is 0.5 - 2.5 MHz.

See section 7.4.8.3 PLL Frequency Limits of the datasheet.

0 Daniel70334 over 11 years ago in reply to Matthijs van Duin

Expert 1745 points

Ah, I see. Thanks!

Do you happen to know why TI wrote a parallel way to control the HDMI PLL in this system.c file, rather than using the normal clk_get(), clk_set_parent(), etc? It seems like they did more work for less functionality - for example, system.c doesn't use FRACTIONALM, so sometimes it estimates too high ...

Dan -

0 Matthijs van Duin over 11 years ago in reply to Daniel70334

Mastermind 8040 points

I have no idea, I'm not really familiar with the video frameworks on the DM814x.

Note BTW that afaik using a fractional PLL multiplier does increase clock jitter; though of course you may have no choice if you can't make the desired frequency without it.

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DM814x video2_pll refclock limitation?