ARM Sitara AM3892 Booting Issue

pramod kashyap said:

We are getting SD clock from ARM Device during POR,

Are you saying that while the POR signal is asserted that you are seeing a clock on the SD interface?  I don't have much experience on this specific device, but in general I would not expect to see that sort of activity while the device is held in reset.

pramod kashyap said:

Please clarify what this means about PORn and RESETn Pins in Data sheet,

( Once the power supplies and the input clock source are stable, the PORn  pin must remain asserted
(low) for a minimum of 32 DEV_MXI cycles and  RESETn pin must be asserted (low) for a minimum of 32 DEV_MXI cycles)

It is just saying that you need to hold the device in reset while the power rails are ramping.  They quantify how long you need to hold it in reset in terms of DEV_MXI cycles.

Please correct your hardware such that  reset stays asserted for 32 DEV_MXI cycles.

First, a quick logistical issue.  Please do not mark all your replies as "suggested answer".  The "suggested answer" is for when someone thinks their response has resolved the issue.  I have unmarked them.  People are less likely to view your thread and offer assistance if it shows as having a suggested answer.

With regard to your responses, I don't think there's further help we can provide through the forum.  If you don't have the expertise to design a power supply that will ramp the supplies in the appropriate order and hold POR asserted for the specified time, then I recommend that you hire someone (e.g. a contractor) to do so.  The power up sequence is well specified in the data manual.

Hello Brad,

Sorry for marking as suggested answer,

then can you clarify this doubt with ARM expertise person in TI ?

Thanks,

Pramod

Hello Brad,

Thanks for help and i will check the power ramp up and PORn signal status,

I will update you if further appropriate help is required

Thanks,

Pramod