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Find detailed descriptions of "I2S Device modes of transmission" of C55x

Other Parts Discussed in Thread: TMS320C5535

In the file 'csl_i2s..h' of CSL (version 3.04), I have some questions to ask. They are about I2S Device modes of transmission.

Between line 216 and 228 are the following code:


In order to understand these codes, I have read "TMS320C5535/34/33/32 Ultra-Low Power DSP Technical Reference Manual“, specifically chapter 1 (system control), 3 (DMA) and 10 (I2S), but I cannot find detailed descriptions about I2S Device modes of transmission.

In my opinion,

1) I2S_POLLED means I2S data is accessed by CPU using polling mode.

2) I2S_INTERRUPT means I2S data is accessed by CPU using interrupt mode.

3)  DMA_POLLED means I2S data is accessed by DMA using polling mode.

4)  DMA_INTERRUPT  means I2S data is accessed by DMA using interrupt mode.

am I right? what is I2S_OPMODE_OTHER mean?

Furthermore, how are  these 5 modes defined, what are differences between them in real applications, and where can I find technical explanations about them. 


Thanks a lot.

  • I paste a snap shot of the code, but it seems that the image cannot be displayed.
    I paste the code again in text format this time as follows:

    /**
    * \brief I2S Device mode of transmission
    *
    * This is used at device open and to configure the I2S device
    */
    typedef enum
    {
    I2S_POLLED, /**< I2S transfer is through I2S polled mode */
    I2S_INTERRUPT, /**< I2S transfer is through I2S intr mode */
    DMA_POLLED, /**< I2S transfer is through DMA polled mode */
    DMA_INTERRUPT, /**< I2S transfer is through DMA intr mode */
    I2S_OPMODE_OTHER /**< Undefined transfer mode */
    }I2S_OpMode;
  • Hi,

    With respect to your understanding on the 4 points you mentioned, Yes its correct. The 5th mode I2S_OPMODE_OTHER is an undefined mode and is not used.

    For details on the DMA and interrupt refer to C5535 TRM  - chapter 1 - System control.

    Following section in System Control chapter provides details on I2S DMA and Interrupts.

    1.7.4.1 DMA Synchronization Events

     

    1.7.4.2 DMA Configuration Registers

     

    1.6 Interrupts


    Hope this information helps.

     

    Regards

     Vasanth