AM335x in reset mode

Hi,

What is your ICE board revision? How do you connect? Have you selected the correct target? Please provide more details.

Hi,
the revision of the board is 1.0A
I connect thru the usb connector
the ccxml file is configured as follows:
Connection: TI XDS100v2 USB Debug Probe
Board or Device: ICE_AM3359
" Test connection" gives the following log:

[Start: Texas Instruments XDS100v2 USB Debug Probe_0]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\NA2264~1.INT\AppData\Local\TEXASI~1\
CCS\ti\1\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Sep 4 2015'.
The library build time was '21:59:23'.
The library package version is '6.0.14.5'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 64 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End: Texas Instruments XDS100v2 USB Debug Probe_0]

This seems correct. How about the target - have you selected Cortex-A8?

Could you precise your question? I'm not sure to understant what I'm expected to do.

What is the target you have selected in Code Composer?

I will plan to update to rev2.1
until then, is there any wort around to get m binary working with rev1.0?

N.AB said:

Do anyoe know how to solve this probe?

The AM335x contains two ARM processors, a Cortex-A8 and a Cortex-M3. The Cortex-A8 is the usual target for downloaded programs, since the Cortex-M3 is intended to only run wakeup (power management) firmware.

The first time a debug session is started on a AM335x ARM based project CCS will display a dialog of the following form, asking which ARM CPU(s) to load the program on:

The default is to load the program onto both the Cortex-A8 and Cortex-M3. If OK is selected with both selected then the load will fail with the following since the Cortex-M3 is held in reset at AM335x reset:

M3_wakeupSS_1: Error connecting to the target: (Error -1266 @ 0x0) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 6.0.14.5)

Once you have started a debug session selecting the default of loading the program on both the Cortex-A8 and Cortex-M3 CCS remembers your choice, and so further attempts to start a debug session fail with the same error.

A solution is to delete the .launches subdirectory within the CCS project directory, which is where CCS stores the debug session properties, and then start a debug session and this time select to only load the program onto the Cortex-A8.