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Why SRIO example project in the Keystone II begin to use PHY-A CMU register to make configuration?

Peter010
Genius 4165 points
Other Parts Discussed in Thread: 66AK2H12

Hello everyone

Previously, the SRIO example project for the 6678 in the PDK package, such that LoopbackDioIsr, and TputBenchmarkingTestProject, use the SerDes Receive/Transmit Channel Configuration Registers listed in the SRIO User Guide to configure the SRIO port width and speed. However, for the SRIO example project of the 66AK2H12 in the pdk_keystone2_3_01_04_07, it use PHY-A CMU register listed in the SerDes User Guide. 

It seems like programming"SerDes Receive/Transmit Channel Configuration Registers" is much more clear and easy. What is the reason of changing the method of configuration.

Or maybe.........

Does it mean that SerDes Receive/Transmit Channel Configuration Registers in the SRIO user guide are not existed in the Keystone II?

  • 0
    TI__Guru* 81335 points

    It seems like programming"SerDes Receive/Transmit Channel Configuration Registers" is much more clear and easy. What is the reason of changing the method of configuration.

    Or maybe.........

    Does it mean that SerDes Receive/Transmit Channel Configuration Registers in the SRIO user guide are not existed in the Keystone II?

    The connectivity is increased from keystone I and II devices. Please refer the keystone I & II serdes document for difference.
    Keystone I SerDes UG ( Implementation Guide): http://www.ti.com/lit/sprabc1
    Keystone II SerDes UG: http://www.ti.com/lit/spruho3

    Thank you.
  • 0 in reply to Raja
    Genius 4165 points

    Hi Raj

    After comparing those two documents your referenced, I found that the PCIe, SRIO, Hyperlink, and etc., are configured through the same SerDes PHY, but not from separate address space as Keystone I. Is that correct?

    And, in the Keystone II SerDes UG, it always keep saying that:"PHY configurations specific to each interface through TI-provided APIs supplied as part of MCSDK", and "Configuration of this PHY interface is handled through the driver code provided in the TI Multicore Software Development Kit (MCSDK) and Chip Support Library (CSL)". Where can I find those driver code for SerDes, and where is the UG for those codes? I have tried to find those answers from the MCSDK User Guide for Keystone II, but I failed. 

    The last, as the SRIO UG is still on the page of Keystone II product site, I am assuming that the SRIO UG is still applied to the Keystone II, isn't it?

    Thanks
    Xining

  • 0 in reply to Peter010
    TI__Guru* 81335 points
    And, in the Keystone II SerDes UG, it always keep saying that:"PHY configurations specific to each interface through TI-provided APIs supplied as part of MCSDK", and "Configuration of this PHY interface is handled through the driver code provided in the TI Multicore Software Development Kit (MCSDK) and Chip Support Library (CSL)". Where can I find those driver code for SerDes, and where is the UG for those codes? I have tried to find those answers from the MCSDK User Guide for Keystone II, but I failed.


    There are some tools for eye diagram and BER sweep under PDK: pdk_keystone2_3_01_04_07\packages\ti\diag\serdes_diag. Look at user guide at docs folder to understand the usage.
  • 0 in reply to Peter010
    TI__Mastermind 28085 points

    Hi,

    I have answered the same question on your another thread, Please refer the below link.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    TI__Guru* 81335 points
    After comparing those two documents your referenced, I found that the PCIe, SRIO, Hyperlink, and etc., are configured through the same SerDes PHY, but not from separate address space as Keystone I. Is that correct?

    The address space of SerDes is different between keystone I & II devices.

    Thank you.