AM3352 LCD (VFD) interface using GPMC

sram

Other Parts Discussed in Thread: AM3352

Hi,

We have interfaced 8 bit LCD (VFD) with AM3352 using GPMC interface. The GPMC signals AD0-AD7 are used for LCD datalines. The interfaced in configured in non_mux mode with address 0x0100 0000, 16Mb with GPMC_csn2. The following code is used to Configure the GPMC pin mux, Clk Confuguration and GPMC configuration. Using CCS 6.1 with Starterware 2.0.1.1

#define LCD_WRITE(x) (*(volatile unsigned char *)(x))
#define LCD_BASE 0x01000000 //(0x10000000)
#define LCD_OFFSET (LCD_BASE + 0x00)

GPMCPinMuxSetup_LCD(); //Pin mux for AD0-AD7, OE,WE,GPMC_nCs2

GPMCClkConfig(); //GMPC Clock configuration

void GPMC_CONFIG_Settings(unsigned int baseAddr,unsigned int csNum)
{
HWREG(baseAddr + GPMC_CONFIG1(csNum))=0x00000000; //
HWREG(baseAddr + GPMC_CONFIG2(csNum))=0x0007080A;
HWREG(baseAddr + GPMC_CONFIG3(csNum))=0;
HWREG(baseAddr + GPMC_CONFIG4(csNum))=0x04020702;
HWREG(baseAddr + GPMC_CONFIG5(csNum))=0x0009090A;
HWREG(baseAddr + GPMC_CONFIG6(csNum))= 0;
HWREG(baseAddr + GPMC_CONFIG7(csNum))=0x00000F00; //address space starts at 0x10000000
HWREG(baseAddr + GPMC_CONFIG7(csNum)) += 0x00000041; //enable fpga cs
}

After doing this, i'm trying to write a byte in the address 0x0100 0000 but the application crashes at this point with undefined handler.

LCD_WRITE(LCD_OFFSET)=0x0c; //Here the code crashes.

Please let me know, if this is the right way to do and also why it crashes when i'm trying to write to GPMC address. Please suggest.

Thanks

over 8 years ago

0 Brad Griffis over 8 years ago

TI__Guru*** 125430 points

How are the other GPMC_CONFIG7 registers configured? I believe the default value of GPMC_CONFIG7_0 is that it is enabled for 256MB. You may have a conflict in your configuration as a result.

0 sram over 8 years ago in reply to Brad Griffis

Intellectual 680 points

Hi Brad,

Thanks for the response.2553.GPMC_REG_DUMP.txt

I checked the default values of all the GPMC_CONFIG7 registers. GPMC_CONFIG7_0 had the value 0x00000F40 which was overlapping with the GPMC_CONFIG7_2 (used for LCD interface) but all other GPMC_CONFIG7 registers have default value of 0x00000F00. I changed the GPMC_CONFIG7_0 to 0x00000F00 before configuring the GPMC_CONFIG7_2 register but still there is no success. Still it crashes while writing to the GPMC_CONFIG7_2 address. Attached is the GPMC register dump default and After GPMC_CONFIG_2 configured for LCD interface. GPMC_CONFIG7_2 is configured for the Address 0x02000000 and 16MB range.

Please review and suggest.

Thanks

Seetaram

0 sram over 8 years ago in reply to sram

Intellectual 680 points

Hi Brad,

As per your inputs, we did the following changes after which it is working now.

1. MMU configuration for this GPMC region to use MMU_MEMTYPE_DEVICE_SHAREABLE and MMU_REGION_NON_SECURE

2. We configured the GPMC timings parameters as per out VFD display timing requirements

With these changes it is working now. Thanks for the inputs.

Regards,

Seetaram

0 Brad Griffis over 8 years ago in reply to sram

TI__Guru*** 125430 points

Great! Thanks for the update.

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AM3352 LCD (VFD) interface using GPMC