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AM335x EtherCAT Master Benchmark Performance

Daisuke Maeda
Guru 19835 points
Other Parts Discussed in Thread: TMDSICE3359, TIDEP0043, SYSBIOS
Our customer tried the benchmark test for EtherCAT Master using TMDSICE3359 in reference to TI Design below.
Acontis EtherCAT Master Stack Reference Design (TIDEP0043)
The benchmark result in the TI Design is as follows.
EtherCAT Master Stack for TI Sitara CPU Family Design Guide
8 EtherCAT Master Benchmark
9 Test Data
The benchmark result of the customer is as follows.
When default MMU settings that the DDR3 memory attribute is non-bufferable are used, it shows the performance that is lower than the TI Design.
SYS_MMU_ENTRY applMmuEntries[] =
{
   {(void *)0x08100000, SYS_MMU_CACHEABLE},   // Non bufferable| Cacheable
I: Process Inputs = 35.5
O: Send Outputs = 36.4
A: Administration = 49.4
M: Send Acyclic Frame = 12.1
When custom MMU settings that the DDR3 memory attribute is bufferable are used, it shows the performance approximately near the TI Design.
SYS_MMU_ENTRY applMmuEntries[] =
{
   {(void *)0x08100000, SYS_MMU_CACHEABLE | SYS_MMU_BUFFERABLE},   // Bufferable| Cacheable
I: Process Inputs = 14.1
O: Send Outputs = 10.8
A: Administration = 9.8
M: Send Acyclic Frame = 1.7
Why do the default settings show bad performance?
Do the optimization method in the custom settings have any problem?
They want to know the MMU settings used in TI Design. If other optimization method is used, they want to know it.
Best regards,
Daisuke
  • 0
    TI__Guru**** 393215 points
    I will forward this to the ISDK team.
  • 0
    TI__Mastermind 32570 points
    Hi Maeda-san,

    DDR MMU settings Cacheable|bufferable sounds correct. Typically using "Bufferable" setting in the memory on which the code is locate helps to increase performance. I don't think there is any other optimization that was used but I will double check with Acontis.

    Thank you,
    Paula
  • 0 in reply to Paula Carrillo
    TI__Mastermind 32570 points
    Hi Maeda-san, we noticed your DDR address is 0x08100000, is this correct? or is a typo? .. DDR address in our demo is 0x81000000. Just want to confirm.
    Thank you,
    Paula
  • 0 in reply to Paula Carrillo
    Guru 19835 points

    Hi Paula-san,

    Thank you for your reply.

    Sorry. 0x08100000 is a typo in my post. 0x81000000 is correct in the source code.

    Best regards,

    Daisuke

  • 0 in reply to Paula Carrillo
    Guru 19835 points

    Hi Paula-san,

    Has there been any progress to double check with Acontis? Have the MMU settings used in TI Design been made sure?

    I really appreciate your cooperation.

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 32570 points
    Hi Maeda-san, it seems default MMU settings were used for benchmarking, in other words not "buffereable" setting for DDR. Could you please let us know which building settings did you use? (specifically which optimization level?)
    thank you,
    Paula
  • 0 in reply to Paula Carrillo
    Guru 19835 points

    Hi Paula-san,

    Thank you for your reply.

    I have asked our customer whether the release configuration which is -O2 optimization level in building settings is used.

    Best regards,

    Daisuke

  • 0 in reply to Paula Carrillo
    Guru 19835 points

    Hi Paula-san,

    Our customer used the release configuration which is -O2 optimization level in building settings, but it shows the performance that is lower than the TI Design.

     SYS_MMU_ENTRY applMmuEntries[] =
     {
     
        {(void *)0x81000000, SYS_MMU_CACHEABLE},   // Non bufferable| Cacheable
     
     I: Process Inputs = 32.9
     O: Send Outputs = 32.9
     A: Administration = 45
     M: Send Acyclic Frame = 9.6

    The software to support in the TI Design is as follows:

     - Acontis EC-Master for SYSBIOS: V2.7.2.12
     - AM335x SYSBIOS Industrial SDK: v1.1.0.8
     - Code Composer Studio: 6.0.0.00040
     - Compiler: v5.1 or higher
     - SYSBIOS: 6.41.04.54
     - XDC: v3.30.06.67 or higher

    The customer uses the following software.

     - Acontis EC-Master for SYSBIOS: V2.7.3.2
     - AM335x SYSBIOS Industrial SDK: v1.1.0.10
     - Code Composer Studio: 6.1.2.00015
     - Compiler: TI v5.2.5
     - SYSBIOS: 6.45.00.35
     - XDC: v3.32.0.06_core

    Why does the benchmark result by customer show bad performance? Does the software version used by customer have a problem?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 32570 points

    Daisuke-san, In order to see if software versions has any impact we would need to re-do profiling..

    A note, Acontis EcMaster library V2.7.2.12 for SYSBIOS was build using optimization O2 and 1.1.0.3 IASDK, but in our TI design we used 1.1.0.8. Your customer could give a try to IASDK 1.1.0.3 as a test.

    A couple of questions:

    - Is your customer using same bus slaves? same frame size? etc.. Different bus and conditions could be the cause of the observed performance differences.

    - Has your customer any issue on using MMU bufferable for DDR section? if not, could they use this attribute to improve performance?. We did a sanity test using EC-Master with DDR "bufferable" and it worked OK. It shouldn't be any drawback on using this memory attribute.

    Thank you,

    Paula

  • 0 in reply to Paula Carrillo
    TI__Mastermind 32570 points

    Hi Daisuke-san, Acontis help us to do a sanity check using EC-Master lib with am335x_sysbios_ind_sdk_1.1.0.8 and am335x_sysbios_ind_sdk_1.1.0.3. They reported that with 1.1.0.8 buffereable gives indeep a performance gain and for 1.1.0.3 buffereable and non-buffereable results are the same performance. We are suspecting for 1.1.0.3 there is bug and memory attribute is always set as buffereable..

    In summary, please suggest your customer to use buffereable. I hope this help to clarify. Thanks for reporting this, for the next EC-Master TI design we will add MMU settings and building optimization flags so it would be easier to reproduce result.

    Thank you,

    Paula

  • 0 in reply to Paula Carrillo
    Guru 19835 points

    Hi Paula-san,

    Thank you for your reply.

    Our customer is going to use v1.1.0.10 with "buffereable" setting for DDR.

    Best regards,

    Daisuke