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AM35x power sequencing

Other Parts Discussed in Thread: AM3505, TPS65023, TPS65073

Hi,

I our application the power sequence is designed as per the Reference Design (SLVA411).
In which VDDS(1.8) is ramped up first and VDDSHV(3.3) next and then VDDS_SRAM_xxx(1.8)
as shown below.

Whereas, the AM3505 datasheet mentions
"VDDS and LDO supplies (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU)
and oscillator supply (VDDSOSC) should come up first to a stable state. "


We can understand the datasheet is the correct one but our design is bit old which
was based on the older version of datasheet(2009) and the Reference Design.
Could you please let us know if this design is wrong and should we re-design the
sequence according to the latest datasheet(which is difficult now)?
Actually all the design guides TPS65073/TPS65023 are as per the older datasheet.

Will it be OK to continue with the older design?

Best Regards
Kummi

  • Hi,

    I will ask the factory team to comment what was the reasoning behind these changes in sequencing.
  • If VDDS is the first powered up, there is no issue in powering VDDS_SRAM_xxx, VDDSOSC later. As also noted in the App note, if there is a common 1.8V powering all these rails, you can also combine them.

    Regards, Siva
  • Hi Biser and Siva,

    Thank you very much for the confirmation. This info is very helpful.
    We shall continue with the below sequence.
    Please let us know if there is anything missing.

    Best Regards
    Kummi.

  • Your sequence looks fine. Make sure you also follow proper power-down requirements as in the data sheet

    Regards, Siva

  • Hi Siva, Biser,

    Thank you for your help in designing the Power-Up sequence.
    We almost finished designing the power-up sequence as per the datasheet and your suggestions

    We need one clarification on the Power-down sequence.

    With respect to the "Option 1: Power down all domains simutaneously",
    Depending upon the capacitors used with the DC/DC or LDO's there may 
    be a slight delay between the power domains and all the power domains may 
    not be powered down at a time.

    In this case I think below E2E (< 2V difference) could be applied. 
    "A strict requirement in the simultaneous power down sequencing is that the voltage difference 
    between 1.8V power rails and 3.3 V power rails can't be more than 2 V. The voltage difference 
    must be kept within < 2V during the power down sequence."
    e2e.ti.com/.../418038

    But in our application(timing sequence in my previous post), 
    the VDDS and VDDSHV power domains may power down earlier and the PLL domains (USBHOST and PER_CORE) 
    may be bit delayed.

    So we need to know that above E2E's "< 2V difference" rule applies only for VDDS and VDDSHV domains
    or does it applies for all the 3.3V and 1.8V domains including PLL domains?

    Best Regards
    Kummi

  • Hi,

    Please let us know if there is any comments on the above power-down sequence.
    We need to finalize our design this week and proceed for Laying out the PCB.
    And your comments will be useful for our design.

    Best Regards
    Kummi
  • If you cannot maintain power down of all the rails at the same time and maintain min. differential voltage between the rails, make sure you turn OFF VDDS supply last. This will also satisfy the VDDSHV rail being < 2V of VDDS.

    Regards, Siva
  • Hi Siva

    Thank you very much for the information.

    One final confirmation,

    Can we assume that  "< 2V difference" rule should strictly be followed for VDDS and VDDSHV rails
    and it won't be critical with respect to other 1.8V rails like Core domain (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU)
    and PLL domains (VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE)?




    As mentioned above there is a possibilty that PLL domains (VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE)
    may be bit delayed but as per your suggestion we can make sure to turn OFF VDDS supply last.

    Best Regards
    Kummi

  • Hi Siva,

    Could you please let me know your comments on the above final confirmation,
    we are already into the PCB design, just wanted to make sure there is no issue in the design.

    Best Regards
    Kummi
  • The 2V requirement is only between VDDS and VDDSHV. Please make sure that VDDS is the last supply per my earlier response.