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AM1705: AM1705 PLL can not initialized correctly

Shine
Genius 13655 points
Part Number: AM1705

Hello Champs, 

Customer would like a schematic review for the AM1705. He made two different designs (with different connections) and both have suffered the same problem of the PLL not initializing correctly. The process correctly executes all code that has been flashed to it as long as it does not enable the PLL.

In the first revision of the design, he had 120ohm ferrite beads on the power supplies with a single 0.1uF. In the second revision he got 60ohm ferrites with a 10uF, 1uF, 0.1uF and 1000pF capacitors. Would the missing 0.01uF capacitor cause this much disruption? 

He can't initialize the PLL in emulation mode. He can get access to the registers but when enabling the PLL, he lose control of the processor.

All of the power supplies are good and the reset pin has a 10k pull up to 3.3V. 

I advise him to change the ferrite beads. Customer changed the capacitors and ferrites, but he is still observing the same thing.

Any advice will be greatly appreciated.

Best Regards

Shine


  • 0
    TI__Mastermind 43660 points
    Shine,

    What is the PLL input clock frequency ? Have you verified the quality of the input clock ?

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    TI__Genius 13655 points
    Hello Senthil,

    Thanks for your quick reply.

    The input clock is 24MHz. Customer has verified it on the first and second revision board and it is a very clean sine signal. 

    The PLL settings are (for future reference) is a multiplier of 25 (24 in the register) for a clock of 600MHz and a post division of 2 (1 in the post_div register) .

    Thanks.

    Rgds
    Shine
  • 0 in reply to Shine
    TI__Mastermind 43660 points

    Shine,

    What error the customer is getting when initialize the PLL ? Can you ask them to intialize the PLL using GEL file and post the error message ?

    Are they seeing this issue on all the boards ?

    If the customer want to request for schematics review, please refer below link.


    Regards,
    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    TI__Genius 13655 points
    Hello Senthil,

    Yes, cusomer can see the error on all of the boards. The error is the following:

    ARM9_0: GEL Output: Flush Instruction Cache
    ARM9_0: GEL Output: Disable MMU
    ARM9_0: GEL Output: Setup PINMUX Registers...ARM9_0: GEL Output: [Done]
    ARM9_0: Trouble Writing Memory Block at 0x1c11100 on Page 0 of Length 0x4
    ARM9_0: GEL: Error while executing OnTargetConnect(): Target failed to write 0x01C11100
    at (*((unsigned int *) (0x01C11000+0x100))|=(CLKMODE<<8)) [evmam1707.gel:296]
    at Setup_PLL() [evmam1707.gel:39]
    at OnTargetConnect()
    ARM9_0: Trouble Reading Register REG_ENDIAN: (Error -150 @ 0x2A33) One of the FTDI driver functions used during configuration returned a invalid status or an error. (Emulation package 6.0.504.1)
    ICEPICK_C: Error: (Error -150 @ 0x0) One of the FTDI driver functions used during configuration returned a invalid status or an error. (Emulation package 6.0.504.1)
    ARM9_0: Trouble Reading Register REG_SYSTEM_TARGET_PSR: (Error -150 @ 0x2A3C) One of the FTDI driver functions used during configuration returned a invalid status or an error. (Emulation package 6.0.504.1)
    ARM9_0: Trouble Reading Register REG_SYSTEM_TARGET_CONFIG: (Error -150 @ 0x2A3C) One of the FTDI driver functions used during configuration returned a invalid status or an error. (Emulation package 6.0.504.1)

    Thanks.

    Rgds
    Shine
  • 0 in reply to Shine
    TI__Mastermind 43660 points
    Shine,

    Could you try access the PLL0_PLLCTL register from CCS register window and try to write the value ?

    Have you tried the gel file on the EVM ? Does it work fine ?

    Please refer below thread where similar issue was discussed.

    e2e.ti.com/.../289397

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    TI__Genius 13655 points

    Hi Senthil,

    Yes customer has  tried changing the value from CCS and the error is the same once the PLL is enabled. 
    But he unfortunately don't have access to the EVM.
    From the comments on the schematic review on that thread, they don't have any resistors in line with the power supplies except for 0 ohm resistors. 
    JTAG lines are terminated as per the wiki. 
    The PLL VDD comes from a switching supply with the mentioned ferrites in line and capacitors as per the data sheet. He can try using an LDO instead if you think it'll work better.
    All the reserved pins are connected as per the datasheet and I've reserved two layers on the board for GND and VDD planes. The bottom layer is used for signals and for the CVDD plane so it is not perfect but should provide enough capacitance as required. 
    The oscillators on both boards are as close to the required pins as can be.

    Thanks.

    Rgds
    Shine