AM5728: IO delay settings

Hi Michi,

1). No, it does not adjust all IO pins. U-boot performs IO delay recalibration only on the pads listed in the core_padconf_array_essential_<board> structure located in mux_data.h. See board/ti/am57xx/board.c:

  if (board_is_am572x_idk()) {

       pconf = core_padconf_array_essential_am572x_idk;

       pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);

       iod = iodelay_cfg_array_am572x_idk;

       iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);

  } else if (board_is_am571x_idk()) {

       pconf = core_padconf_array_essential_am571x_idk;

       pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);

       iod = iodelay_cfg_array_am571x_idk;

       iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);

  } else {

 /* Common for X15/GPEVM */

       pconf = core_padconf_array_essential_x15;

       pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);

/* There never was an SR1.0 X15.. So.. */

      if (omap_revision() == DRA752_ES1_1) {

              iod = iodelay_cfg_array_x15_sr1_1;

              iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);

       } else {

/* Since full production should switch to SR2.0  */

              iod = iodelay_cfg_array_x15_sr2_0;

              iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);

      }

}

2). See Section 18.4.6.1.8 IO Delay Recalibration of AM572x TRM. You'll see that there are registers indicating the start of the io recalibration sequence & the completion of the io recalibration sequence. You can monitor those to see if the procedure have started/completed.

3). Yes, your understanding is correct.  See Section 18.4.6.1.1 Pad Configuration Registers of the device TRM:

  "After POR, software must set the pad configuration registers to appropriate values depending on the desired device configuration. Configuration of the pad configuration registers is normally done as part of the IO delay recalibration sequence described in Section 18.4.6.1.8, IO Delay Recalibration"

And the IO Delay Recalibration sequence is as follows:

  1. Complete the AVS voltage change on the VDD_CORE_L voltage domain and ensure voltage has stabilized to the new AVS target voltage

  2. Unlock the registers used

  3. Perform IO Delay Calibration

  4. Isolate the device IOs via the Isolation Sequence described in Section 18.4.6.1.7 Isolation Requirements

  5. Update the delay mechanism for each IO with new calibrated values

  6. Configure the pad configuration register (CTRL_CORE_PAD_x) for each IO with the desired MUXMODE, DELAYMODE, and MODESELECT settings.

  7. Configure all required Manual IO Timing Modes as described in Section 18.4.6.1.6, Manual IO Timing Modes

  8. De-isolate the device IOs via the de-isolation sequence described in Section 18.4.6.1.7 Isolation Requirements

  9. Relock the registers

Hope this helps. 

Best Regards, 
Yordan

Do you mean software must define the CORE PAD register for IO delay recalibration? I thought IO delay recalibration is harware feature of AM5728. So all IO pins are calibratted by automatic (by writing CONFIG_REG_0 [0] bit to 1).

do all IO pins that customer uses have to define by entry table like "pad_conf_entry core_padconf_array_essential_x15"?

Hi Michi,

3. Perform IO Delay Calibration ----------> I think the definition of pad configuration is not needed in this step. Is my understanding right?
5. Update the delay mechanism for each IO with new calibrated values:
(a) Write 1 to register field CONFIG_REG_0[1] ROM_READ of the IODELAYCONFIG module to initiate a reload of calibrated delay values for all IOs. ----------> I think the delay value of all IOs is written with new calibrated values by writing 1 to CONFIG_REG_0[1]bit. In other words, IO delay calibration is executed to all IOs automatically. So In this step, the definition of pad configuration is not needed. Is my understanding right?