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TMS320C6412: XIO2001 PCIe bridge performance

Part Number: TMS320C6412
Other Parts Discussed in Thread: XIO2001

I have a design with a XIO2001 PCIe to PCI bridge to a C6412. We see >100MBps when doing bursts which is ok when we're operating the PCI bus at 33MHz but we see the same throughput when we operate the PCI bus at 66MHz. We would have expected something closer to 200MBps in that mode. I've confirmed the various pull-ups and downs are correct and that the PCI clock is at 66MHz.

We use the C6412 PCI DMA engine to transfer from L2 SRAM to the host PC. We get similar rates from the DSP's off-chip SDRAM. Reading through the forums I found the XIO2001 Performance Tuner and will be trying that tomorrow but it seems most of the other threads are concerned with getting over 100MBps with a 33MHz clock and we already have that.

  • Hi Shawn,

    I've forwarded this to the experts. Their feedback should be posted here.

    Tsvetolin Shulev
  • Shawn,

    Support is very limited for this device which is over 10 years old.  Why are you developing with this old device rather than a newer device from the C66xx DSP family which has active support?

    Your question is probably resolved by proper software tuning assuming that the device can even support the throughput that you desire.  This information is probably not available.


  • Hi Tom,

    Thanks for the quick response. We have a lot of legacy code running on this DSP and actually the design is a few years old already. However throughput has recently become an issue and downloads from this module are the limiting factor. Updating to a new DSP is planned in the future but we have a large install base with this design.

    As near as I can tell from the documentation the higher rates at 66MHz should be possible. We'll try the tuner to see if that helps.


  • Hi Shawn
    Don't have much additional information to offer here, as Tom said this is a very old device and support is limited.
    I have to assume you are looking at the following application note

    If you are, please make sure you understand where you can get double the throughput etc (size of transfers, source/destination memory etc all factor in - and may not scale the same way as PCI clock going from 33 to 66)
    hope this helps some.

  • That document is what led me to believe we can reach >200MBps with 66MHz. Or at least above 133MBps.
    Today we used the XIO2001 performance tool but we were not able to affect performance meaningfully with that other than finding a few states to avoid.
    We continued investigating though and found a bug in our DMA driver code that was adding overhead that we weren't accounting for in our benchmarks. We're up to 180MBps from L2 and 140MBps from the on-board SRAM we ultimately need to download from. We're going to look for more overhead reductions and the SRAM timing but now that we're over 133MBps we think the bus configuration is correct.
    Thanks for your help Mukul and Tom.