Team,
My customer has the following question.
We are performing a Hyperlynx simulation to verify DDR2 timing for a new design, and are running into timing issues. The architecture uses a two chip Balanced T routing with 22 ohm series terminations, and meets all layout guidelines and length matching requirements specified by the TI documentation. We have found that the simulation model can pass by adding a parallel termination to Vtt right after the T junction of the routing, which is a standard termination scheme for DD2 architectures. However, the TI documentation explicitly says that this termination scheme is not allowed and I am trying to understand why. See the datasheet excerpt below.
