Part Number: DRA722
Other Parts Discussed in Thread: DRA72
Tool/software: Linux
Hi all,
There is an error with video input capture hanged when I use gst-launch-1.0 to capture video source.
Currently we use J6 eco custom board with GLSDK 3.00.00.03.
We use ov10633 to be video intput decoder.
The below is my log and DTS
log file:
U-Boot SPL 2016.05 (May 22 2017 - 12:45:39) DRA722-GP ES1.0 MMC Device 1 not found *** Warning - No MMC card found, using default environment Trying to boot from MMC1 MMC Device 1 not found *** Warning - No MMC card found, using default environment reading u-boot.img reading u-boot.img U-Boot 2016.05 (May 22 2017 - 12:45:39 +0800) CPU : DRA722-GP ES1.0 Board: DRA72x EVM REV <NULL> I2C: ready DRAM: 1 GiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 *** Warning - bad CRC, using default environment Warning: fastboot.board_rev: unknown board revision GUID Partition Table Header signature is wrong: 0x0 != 0x5452415020494645 part_get_info_efi: *** ERROR: Invalid GPT *** GUID Partition Table Header signature is wrong: 0x0 != 0x5452415020494645 part_get_info_efi: *** ERROR: Invalid Backup GPT *** ERROR: cannot find partition: 'userdata' at arch/arm/cpu/armv7/omap-common/utils.c:195/mmc_get_part_size() Warning: fastboot.userdata_size: unable to calc i2c_write: error waiting for addr ACK (status=0x116) SCSI: Net: <ethaddr> not set. Validating first E-fuse MAC Could not get PHY for cpsw: addr 3 cpsw Hit any key to stop autoboot: 0 J6E ... switch to partitions #0, OK mmc0 is current device SD/MMC found on device 0 3736416 bytes read in 336 ms (10.6 MiB/s) 102151 bytes read in 32 ms (3 MiB/s) Booting from mmc0 ... Kernel image @ 0x82000000 [ 0x000000 - 0x390360 ] ## Flattened Device Tree blob at 88000000 Booting using the fdt blob at 0x88000000 Loading Device Tree to 8ffe4000, end 8fffff06 ... OK Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Initializing cgroup subsys cpuset [ 0.000000] Initializing cgroup subsys cpu [ 0.000000] Initializing cgroup subsys cpuacct [ 0.000000] Linux version 4.4.14 (root@louis-VirtualBox) (gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03) ) #5 SMP PREEMPT Mon May 22 18:26:32 CST 2017 [ 0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache [ 0.000000] Machine model: TI DRA722 Louis 20170516 13:50 [ 0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB [ 0.000000] Reserved memory: initialized node ipu2_cma@95800000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB [ 0.000000] Reserved memory: initialized node dsp1_cma@99000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB [ 0.000000] Reserved memory: initialized node ipu1_cma@9d000000, compatible id shared-dma-pool [ 0.000000] cma: Reserved 24 MiB at 0x00000000be000000 [ 0.000000] Forcing write-allocate cache policy for SMP [ 0.000000] Memory policy: Data cache writealloc [ 0.000000] OMAP4: Map 0x00000000bfd00000 to fe600000 for dram barrier [ 0.000000] DRA722 ES1.0 [ 0.000000] PERCPU: Embedded 12 pages/cpu @ef644000 s19008 r8192 d21952 u49152 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 258368 [ 0.000000] Kernel command line: console=ttyO2,115200n8 root=PARTUUID=4320892c-02 rw rootfstype=ext4 rootwait omapdrm.num_crtc=2 drm.debug=0xff [ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes) [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [ 0.000000] Memory: 839120K/1040384K available (6663K kernel code, 364K rwdata, 2512K rodata, 356K init, 293K bss, 21040K reserved, 180224K cma-reserved, 233472K highmem) [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB) [ 0.000000] vmalloc : 0xf0800000 - 0xff800000 ( 240 MB) [ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB) [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) [ 0.000000] .text : 0xc0008000 - 0xc08fe084 (9177 kB) [ 0.000000] .init : 0xc08ff000 - 0xc0958000 ( 356 kB) [ 0.000000] .data : 0xc0958000 - 0xc09b3150 ( 365 kB) [ 0.000000] .bss : 0xc09b5000 - 0xc09fe618 ( 294 kB) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 [ 0.000000] Preemptible hierarchical RCU implementation. [ 0.000000] Build-time adjustment of leaf fanout to 32. [ 0.000000] RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1. [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=1 [ 0.000000] NR_IRQS:16 nr_irqs:16 16 [ 0.000000] OMAP clockevent source: timer1 at 31475 Hz [ 0.000000] Architected cp15 timer(s) running at 5.90MHz (virt). [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x15c70fb29, max_idle_ns: 440795202138 ns [ 0.000005] sched_clock: 56 bits at 5MHz, resolution 169ns, wraps every 4398046511093ns [ 0.000015] Switching to timer-based delay loop, resolution 169ns [ 0.000334] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns [ 0.000342] OMAP clocksource: 32k_counter at 32768 Hz [ 0.000758] Console: colour dummy device 80x30 [ 0.000775] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2' [ 0.000782] This ensures that you still see kernel messages. Please [ 0.000787] update your kernel commandline. [ 0.000800] Calibrating delay loop (skipped), value calculated using timer frequency.. 11.80 BogoMIPS (lpj=59016) [ 0.000811] pid_max: default: 32768 minimum: 301 [ 0.000903] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) [ 0.000914] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) [ 0.001430] Initializing cgroup subsys io [ 0.001448] Initializing cgroup subsys memory [ 0.001470] Initializing cgroup subsys devices [ 0.001482] Initializing cgroup subsys freezer [ 0.001493] Initializing cgroup subsys perf_event [ 0.001504] Initializing cgroup subsys pids [ 0.001526] CPU: Testing write buffer coherency: ok [ 0.001725] /cpus/cpu@0 missing clock-frequency property [ 0.001737] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 0.001773] Setting up static identity map for 0x80008380 - 0x800083d8 [ 0.050026] Brought up 1 CPUs [ 0.050037] SMP: Total of 1 processors activated (11.80 BogoMIPS). [ 0.050044] CPU: All CPU(s) started in SVC mode. [ 0.050352] devtmpfs: initialized [ 0.080041] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0 [ 0.080983] omap_hwmod: l3_main_2 using broken dt data from ocp [ 0.266003] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns [ 0.273601] pinctrl core: initialized pinctrl subsystem [ 0.274510] NET: Registered protocol family 16 [ 0.275457] DMA: preallocated 256 KiB pool for atomic coherent allocations [ 0.300197] cpuidle: using governor ladder [ 0.330224] cpuidle: using governor menu [ 0.338896] OMAP GPIO hardware version 0.1 [ 0.342833] GPIO line 161 (radio_rst) hogged as output/low [ 0.345078] irq: no irq domain found for /ocp/l4@4a000000/scm@2000/pinmux@1400 ! [ 0.369108] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers. [ 0.369119] hw-breakpoint: maximum watchpoint size is 8 bytes. [ 0.369528] omap4_sram_init:Unable to allocate sram needed to handle errata I688 [ 0.369538] omap4_sram_init:Unable to get sram pool needed to handle errata I688 [ 0.370128] OMAP DMA hardware revision 0.0 [ 0.444060] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver [ 0.445176] edma 43300000.edma: memcpy is disabled [ 0.449992] edma 43300000.edma: TI EDMA DMA engine driver [ 0.453428] omap-iommu 40d01000.mmu: 40d01000.mmu registered [ 0.453610] omap-iommu 40d02000.mmu: 40d02000.mmu registered [ 0.453768] omap-iommu 58882000.mmu: 58882000.mmu registered [ 0.453918] omap-iommu 55082000.mmu: 55082000.mmu registered [ 0.455899] SCSI subsystem initialized [ 0.460751] usbcore: registered new interface driver usbfs [ 0.460807] usbcore: registered new interface driver hub [ 0.460874] usbcore: registered new device driver usb [ 0.461960] palmas 0-0058: could not find pctldev for node /ocp/l4@4a000000/scm@2000/pinmux@1400/tps65917_pins_default, deferring probe [ 0.480574] pcf857x: probe of 0-0020 failed with error -121 [ 0.480845] pcf857x: probe of 0-0021 failed with error -121 [ 0.481003] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz [ 0.481424] omap_i2c 48060000.i2c: bus 2 rev0.12 at 400 kHz [ 0.500597] pcf857x: probe of 3-0021 failed with error -121 [ 0.500635] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz [ 0.520612] pcf857x: probe of 4-0026 failed with error -121 [ 0.520936] pca953x 4-0020: failed reading register [ 0.520954] pca953x: probe of 4-0020 failed with error -121 [ 0.521105] omap_i2c 4807c000.i2c: bus 4 rev0.12 at 400 kHz [ 0.521275] media: Linux media interface: v0.10 [ 0.521326] Linux video capture interface: v2.00 [ 0.521364] pps_core: LinuxPPS API ver. 1 registered [ 0.521371] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> [ 0.521394] PTP clock support registered [ 0.521421] EDAC MC: Ver: 3.0.0 [ 0.531111] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400 [ 0.531307] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400 [ 0.532439] clocksource: Switched to clocksource arch_sys_counter [ 0.542617] NET: Registered protocol family 2 [ 0.543125] TCP established hash table entries: 8192 (order: 3, 32768 bytes) [ 0.543197] TCP bind hash table entries: 8192 (order: 4, 65536 bytes) [ 0.543328] TCP: Hash tables configured (established 8192 bind 8192) [ 0.543380] UDP hash table entries: 512 (order: 2, 16384 bytes) [ 0.543411] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) [ 0.543596] NET: Registered protocol family 1 [ 0.553889] RPC: Registered named UNIX socket transport module. [ 0.553899] RPC: Registered udp transport module. [ 0.553906] RPC: Registered tcp transport module. [ 0.553912] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 0.554951] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available [ 0.557020] futex hash table entries: 256 (order: 2, 16384 bytes) [ 0.574795] squashfs: version 4.0 (2009/01/31) Phillip Lougher [ 0.585484] NFS: Registering the id_resolver key type [ 0.585512] Key type id_resolver registered [ 0.585520] Key type id_legacy registered [ 0.585593] ntfs: driver 2.1.32 [Flags: R/O]. [ 0.587894] bounce: pool size: 64 pages [ 0.588056] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 248) [ 0.588070] io scheduler noop registered [ 0.588081] io scheduler deadline registered [ 0.588111] io scheduler cfq registered (default) [ 0.592875] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128 [ 0.593004] pinctrl-single 4a002e8c.pinmux: 1 pins at pa fc002e8c size 4 [ 0.596098] PCI host bridge /ocp/axi@0/pcie@51000000 ranges: [ 0.596110] No bus range found for /ocp/axi@0/pcie@51000000, using [bus 00-ff] [ 0.596143] IO 0x20003000..0x20012fff -> 0x00000000 [ 0.596164] MEM 0x20013000..0x2fffffff -> 0x20013000 [ 0.606403] dra7-pcie 51000000.pcie: PCI host bridge to bus 0000:00 [ 0.606417] pci_bus 0000:00: root bus resource [bus 00-ff] [ 0.606428] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] [ 0.606437] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff] [ 0.606847] PCI: bus0: Fast back to back transfers disabled [ 0.622524] PCI: bus1: Fast back to back transfers disabled [ 0.622579] irq: no irq domain found for /ocp/axi@0/pcie@51000000/interrupt-controller ! [ 0.622622] irq: no irq domain found for /ocp/axi@0/pcie@51000000/interrupt-controller ! [ 0.622659] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff] [ 0.622674] pci 0000:00:00.0: BAR 8: assigned [mem 0x20200000-0x202fffff] [ 0.622685] pci 0000:00:00.0: BAR 9: assigned [mem 0x20300000-0x203fffff pref] [ 0.622696] pci 0000:00:00.0: BAR 1: assigned [mem 0x20020000-0x2002ffff] [ 0.622708] pci 0000:00:00.0: BAR 7: assigned [io 0x1000-0x1fff] [ 0.622723] pci 0000:01:00.0: BAR 6: assigned [mem 0x20300000-0x2033ffff pref] [ 0.622734] pci 0000:01:00.0: BAR 0: assigned [mem 0x20200000-0x2021ffff] [ 0.622754] pci 0000:01:00.0: BAR 1: assigned [mem 0x20220000-0x2022ffff] [ 0.622774] pci 0000:01:00.0: BAR 3: assigned [mem 0x20230000-0x20233fff] [ 0.622794] pci 0000:01:00.0: BAR 2: assigned [io 0x1000-0x101f] [ 0.622814] pci 0000:00:00.0: PCI bridge to [bus 01] [ 0.622824] pci 0000:00:00.0: bridge window [io 0x1000-0x1fff] [ 0.622835] pci 0000:00:00.0: bridge window [mem 0x20200000-0x202fffff] [ 0.622846] pci 0000:00:00.0: bridge window [mem 0x20300000-0x203fffff pref] [ 0.623072] pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt [ 0.623082] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt [ 0.679871] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled [ 0.683480] 4806a000.serial: ttyS0 at MMIO 0x4806a000 (irq = 301, base_baud = 3000000) is a 8250 [ 0.684373] 4806c000.serial: ttyS1 at MMIO 0x4806c000 (irq = 302, base_baud = 3000000) is a 8250 [ 0.685235] console [ttyS2] disabled [ 0.685282] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 303, base_baud = 3000000) is a 8250 [ 1.773057] console [ttyS2] enabled [ 1.777435] 48066000.serial: ttyS4 at MMIO 0x48066000 (irq = 304, base_baud = 3000000) is a 8250 [ 1.787165] 48068000.serial: ttyS5 at MMIO 0x48068000 (irq = 305, base_baud = 3000000) is a 8250 [ 1.796842] 48424000.serial: ttyS8 at MMIO 0x48424000 (irq = 306, base_baud = 3000000) is a 8250 [ 1.806515] 4ae2b000.serial: ttyS9 at MMIO 0x4ae2b000 (irq = 307, base_baud = 3000000) is a 8250 [ 1.816547] [drm] Initialized drm 1.1.0 20060810 [ 1.822238] omapdss_dss 58000000.dss: master bind failed: -517 [ 1.829804] panel-dpi display@2: failed to find video source [ 2.006300] brd: module loaded [ 2.094614] loop: module loaded [ 2.104158] m25p80 spi32766.0: unrecognized JEDEC id bytes: 00, 0, 0 [ 2.111679] libphy: Fixed MDIO Bus: probed [ 2.117416] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 2.124306] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 2.130864] ehci-pci: EHCI PCI platform driver [ 2.135438] ehci-omap: OMAP-EHCI Host Controller driver [ 2.141012] usbcore: registered new interface driver usbserial [ 2.147206] mousedev: PS/2 mouse device common for all mice [ 2.163491] i2c /dev entries driver [ 2.167687] ov1063x 4-0037: ov1063x Product ID 0 Manufacturer ID 0 [ 2.173946] ov1063x 4-0037: ov1063x 4-0037 sensor driver registered !! [ 2.180684] ov490 4-0024: Failed reading register 0x300a! [ 2.186135] ov490: probe of 4-0024 failed with error -121 [ 2.192290] vpe 489d0000.vpe: loading firmware vpdma-1b8.bin [ 2.198338] pinctrl-single 4a003400.pinmux: pin 4a00363c.0 already requested by 4806a000.serial; cannot claim for 48970000.vip [ 2.209801] pinctrl-single 4a003400.pinmux: pin-143 (48970000.vip) status -22 [ 2.217160] vpe 489d0000.vpe: Device registered as /dev/video0 [ 2.223045] pinctrl-single 4a003400.pinmux: could not request pin 143 (4a00363c.0) from group pinmux_vin2a_pins on device pinctrl-single [ 2.235474] vip 48970000.vip: Error applying setting, reverse things back [ 2.242373] pinctrl-single 4a003400.pinmux: pin 4a00363c.0 already requested by 4806a000.serial; cannot claim for 48970000.vip [ 2.253832] pinctrl-single 4a003400.pinmux: pin-143 (48970000.vip) status -22 [ 2.261000] pinctrl-single 4a003400.pinmux: could not request pin 143 (4a00363c.0) from group pinmux_vin2a_pins on device pinctrl-single [ 2.273411] vip 48970000.vip: Error applying setting, reverse things back [ 2.281239] vip 48970000.vip: loading firmware vpdma-1b8.bin [ 2.290713] omap_hsmmc 4809c000.mmc: Got CD GPIO [ 2.302474] vip 48970000.vip: VPDMA firmware loaded [ 2.307490] vip1-s1: Port A: Using subdev ov1063x 4-0037 for capture [ 2.314085] vip1-s1: device registered as video1 [ 2.372794] omap_hsmmc 480d1000.mmc: no pinctrl state for hs mode [ 2.413189] ledtrig-cpu: registered to indicate activity on CPUs [ 2.419264] mmc0: MAN_BKOPS_EN bit is not set [ 2.423844] usbcore: registered new interface driver usbhid [ 2.429438] usbhid: USB HID core driver [ 2.435093] hwspinlock_user gatemp: requested 10 hwspinlocks [ 2.442527] NET: Registered protocol family 10 [ 2.457696] sit: IPv6 over IPv4 tunneling driver [ 2.462945] NET: Registered protocol family 17 [ 2.467634] Key type dns_resolver registered [ 2.472027] omap_voltage_late_init: Voltage driver support not added [ 2.478979] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.oppdm [ 2.485209] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.oppdm [ 2.491443] ti_oppdm 4a003b20.oppdm: Unable to get vdd regulator:-517 [ 2.498056] Power Management for TI OMAP4+ devices. [ 2.503208] Registering SWP/SWPB emulation handler [ 2.510830] dmm 4e000000.dmm: initialized all PAT entries [ 2.537310] pinctrl-single 4a003400.pinmux: pin 4a003824.0 already requested by 4806a000.serial; cannot claim for 0-0058 [ 2.548314] mmc0: new high speed MMC card at address 0001 [ 2.554087] pinctrl-single 4a003400.pinmux: pin-265 (0-0058) status -22 [ 2.560734] pinctrl-single 4a003400.pinmux: could not request pin 265 (4a003824.0) from group tps65917_pins_default on device pinctrl-single [ 2.573632] palmas 0-0058: Error applying setting, reverse things back [ 2.580250] palmas 0-0058: Irq flag is 0x00000000 [ 2.585020] mmcblk0: mmc0:0001 R1J55A 7.28 GiB [ 2.591936] palmas 0-0058: Muxing GPIO 51, PWM 0, LED 2 [ 2.599868] mmcblk0boot0: mmc0:0001 R1J55A partition 1 128 KiB [ 2.616410] mmcblk0boot1: mmc0:0001 R1J55A partition 2 128 KiB [ 2.623748] mmcblk0: p1 p2 [ 2.629048] OMAP DSS rev 6.1 [ 2.635462] omapdss_dss 58000000.dss: bound 58001000.dispc (ops dispc_component_ops) [ 2.646062] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 2.652899] omap_hsmmc 4809c000.mmc: Got CD GPIO [ 2.692889] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.oppdm [ 2.699100] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.oppdm [ 2.705836] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.oppdm [ 2.712045] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.oppdm [ 2.723709] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 2.730348] [drm] No driver support for vblank timestamp query. [ 2.746683] [drm] Enabling DMM ywrap scrolling [ 2.753011] mmc1: host does not support reading read-only switch, assuming write-enable [ 2.753068] mmc1: new SDHC card at address 1234 [ 2.764227] mmcblk1: mmc1:1234 SA04G 3.71 GiB [ 2.765374] mmcblk1: p1 [ 2.802039] Console: switching to colour frame buffer device 240x67 [ 2.844124] omapdrm omapdrm.0: fb0: omapdrm frame buffer device [ 2.854444] mmc2: host does not support reading read-only switch, assuming write-enable [ 2.862568] mmc2: new SDHC card at address 0001 [ 2.872791] [drm] Initialized omapdrm 1.0.0 20110917 on minor 0 [ 2.879408] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 2.885580] mmcblk2: mmc2:0001 SD4GB 3.64 GiB [ 2.890898] hctosys: unable to open rtc device (rtc0) [ 2.896081] mmcblk2: p1 p2 [ 2.899839] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 2.916703] aic_dvdd: disabling [ 2.920199] ldo4: disabling [ 3.282868] EXT4-fs (mmcblk2p2): recovery complete [ 3.290304] EXT4-fs (mmcblk2p2): mounted filesystem with ordered data mode. Opts: (null) [ 3.298470] VFS: Mounted root (ext4 filesystem) on device 179:66. [ 3.307013] devtmpfs: mounted [ 3.310177] Freeing unused kernel memory: 356K (c08ff000 - c0958000) [ 3.316578] This architecture does not have kernel memory protection. INIT: version 2.88 booting Starting udev [ 4.020365] udevd[109]: starting version 182 [ 4.357507] omap-rproc 58820000.ipu: assigned reserved memory node ipu1_cma@9d000000 [ 4.508199] remoteproc0: 58820000.ipu is available [ 4.619507] remoteproc0: Note: remoteproc is still under development and considered experimental. [ 4.852492] remoteproc0: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed. [ 5.002803] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 5.009078] remoteproc0: Direct firmware load for dra7-ipu1-fw.xem4 failed with error -2 [ 5.022327] omap_rng 48090000.rng: OMAP Random Number Generator ver. 20 [ 5.071946] omap-des 480a5000.des: OMAP DES hw accel rev: 2.2 [ 5.079021] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 5.102049] remoteproc0: failed to load dra7-ipu1-fw.xem4 [ 5.141457] alg: skcipher: setkey failed on test 5 for ecb-des-omap: flags=100 [ 5.252280] alg: skcipher-ddst: setkey failed on test 5 for ecb-des-omap: flags=100 [ 5.343028] alg: skcipher-ddst: setkey failed on test 5 for ecb-des-omap: flags=100 [ 5.481947] 491, r3003 = 17 , r3004 = 23 [ 5.531808] ov1063x 4-0037: r3003 = 17 , r3004 = 23 [ 5.542213] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 5.549580] omap_rtc 48838000.rtc: rtc core: registered 48838000.rtc as rtc0 [ 5.592217] 574, width x height = 720 x 480 [ 5.598920] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 5.608033] omap-rproc 55020000.ipu: assigned reserved memory node ipu2_cma@95800000 udevd[347]: failed to execute '/etc/udev/scripts/mount.sh' '/etc/udev/scripts/mount.sh': No such file or directory[ 5.695786] ov1063x 4-0037: width x height = 720 x 480 udevd[348]: failed to execute '/etc/udev/scripts/mount.sh' '/etc/udev/scripts/mount.sh': No such file or directory [ 5.729246] remoteproc1: 55020000.ipu is available [ 5.779414] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 5.842362] 590, hts x vts = 1083 x 530 udevd[362]: failed to execute '/etc/udev/scripts/mount.sh' '/etc/udev/scripts/mount.sh': No such file or directory[ 5.854316] remoteproc1: Note: remoteproc is still under development and considered experimental. [ 5.887191] CAN device driver interface [ 5.930760] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k [ 5.939657] ov1063x 4-0037: hts x vts = 1083 x 530 [ 6.011964] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. [ 6.069110] e1000e 0000:01:00.0: enabling device (0140 -> 0142) [ 6.106211] remoteproc1: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed. [ 6.130157] e1000e 0000:01:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode [ 6.173115] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 6.179485] omap-aes 4b500000.aes: OMAP AES hw accel rev: 3.3 [ 6.191109] e1000e 0000:01:00.0 0000:01:00.0 (uninitialized): Failed to initialize MSI-X interrupts. Falling back to MSI interrupts. [ 6.387710] e1000e 0000:01:00.0 eth0: registered PHC clock [ 6.417169] e1000e 0000:01:00.0 eth0: (PCI Express:2.5GT/s:Width x1) 88:88:88:88:87:88 [ 6.456674] e1000e 0000:01:00.0 eth0: Intel(R) PRO/1000 Network Connection [ 6.491945] e1000e 0000:01:00.0 eth0: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF [ 6.526584] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 6.653289] omap-aes 4b700000.aes: OMAP AES hw accel rev: 3.3 [ 6.659788] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 6.679773] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec [ 6.690970] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 6.722612] omap-sham 4b101000.sham: hw accel on OMAP rev 4.3 [ 6.745054] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 6.802653] remoteproc1: registered virtio0 (type 7) deuvd[416]: failed to execute '/etc/udev/scripts/mount.sh' '/etc/dev/scripts/mount.sh': No such file or directory udevd[419]: failed to execute '/etc/udev/scripts/mount.sh' '/etc/udev/scripts/mount.sh': No such file or directory [ 7.231353] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 7.274716] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 7.281341] ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x0 impl platform mode [ 7.302505] ahci 4a140000.sata: flags: 64bit ncq sntf pm led clo only pmp pio slum part ccc apst [ 7.333094] scsi host0: ahci [ 7.342544] ata1: DUMMY [ 7.345629] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 7.352543] c_can_platform 4ae3c000.can: c_can_platform device registered (regs=fce3c000, irq=358) [ 7.373102] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 7.382672] omap-rproc 40800000.dsp: assigned reserved memory node dsp1_cma@99000000 [ 7.390494] remoteproc2: 40800000.dsp is available [ 7.412487] remoteproc2: Note: remoteproc is still under development and considered experimental. [ 7.421501] remoteproc2: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed. [ 7.453559] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 7.476107] [drm] Initialized pvr 1.14.3699939 20110701 on minor 1 [ 7.493234] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 7.557381] remoteproc2: registered virtio1 (type 7) [ 7.573429] remoteproc1: powering up 55020000.ipu [ 7.582302] remoteproc1: Booting fw image dra7-ipu2-fw.xem4, size 3484972 [ 7.602525] omap-iommu 55082000.mmu: 55082000.mmu: version 2.1 [ 7.643225] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 7.676239] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller [ 7.681772] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1 [ 7.702788] xhci-hcd xhci-hcd.0.auto: hcc params 0x0220f04c hci version 0x100 quirks 0x00010010 [ 7.711571] xhci-hcd xhci-hcd.0.auto: irq 469, io mem 0x48890000 [ 7.727050] remoteproc1: remote processor 55020000.ipu is now up [ 7.734120] hub 1-0:1.0: USB hub found [ 7.738766] virtio_rpmsg_bus virtio0: rpmsg host is online [ 7.744335] virtio_rpmsg_bus virtio0: creating channel rpmsg-rpc addr 0x3b [ 7.751459] hub 1-0:1.0: 1 port detected [ 7.756000] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 7.763054] remoteproc2: powering up 40800000.dsp [ 7.769020] remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size 929770 [ 7.776313] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller [ 7.781831] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2 [ 7.790978] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 7.803449] omap_hwmod: mmu0_dsp1: _wait_target_disable failed [ 7.809342] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0 [ 7.815271] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0 [ 7.821224] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. [ 7.830240] hub 2-0:1.0: USB hub found [ 7.834074] hub 2-0:1.0: 1 port detected [ 7.838656] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 7.845066] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller [ 7.850588] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 3 [ 7.863096] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 7.882752] xhci-hcd xhci-hcd.1.auto: hcc params 0x0220f04c hci version 0x100 quirks 0x00010010 [ 7.891534] xhci-hcd xhci-hcd.1.auto: irq 470, io mem 0x488d0000 [ 7.913374] hub 3-0:1.0: USB hub found [ 7.922496] hub 3-0:1.0: 1 port detected [ 7.927136] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 7.933592] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller [ 7.939109] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 4 [ 7.952950] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 7.967429] remoteproc2: remote processor 40800000.dsp is now up [ 7.973673] usb usb4: We don't know the algorithms for LPM for this host, disabling LPM. [ 7.982321] virtio_rpmsg_bus virtio1: rpmsg host is online [ 7.987885] virtio_rpmsg_bus virtio1: creating channel rpmsg-client-sample addr 0x36 [ 7.996524] hub 4-0:1.0: USB hub found [ 8.000318] hub 4-0:1.0: 1 port detected [ 8.004485] virtio_rpmsg_bus virtio1: creating channel rpmsg-client-sample addr 0x37 [ 8.012940] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 8.019951] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 8.029190] virtio_rpmsg_bus virtio1: creating channel rpmsg-rpc addr 0x3b [ 8.082188] rpmsg_rpc rpmsg0: probing service rpmsg-dce with src 1024 dst 59 [ 8.099703] rpmsg_rpc rpmsg3: probing service rpmsg-dce-dsp with src 1024 dst 59 [ 8.108407] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 8.115545] cpsw 48484000.ethernet: gpio request failed, ret -517 [ 8.123565] rpmsg_rpc rpmsg3: published functions = 8 [ 8.140241] rpmsg_rpc rpmsg0: published functions = 8 [ 8.168248] EXT4-fs (mmcblk2p2): re-mounted. Opts: (null) Starting Bootlog daemon: bootlogd. [ 8.250460] random: dd urandom read with 65 bits of entropy available ALSA: Restoring mixer settings... /usr/sbin/alsactl: load_state:1729: No soundcards found... Thu Sep 3 18:41:00 UTC 2015 omapconf: powerdm_deinit(): cpu not supported!!! omapconf: clockdm_deinit(): cpu not supported!!! /etc/rcS.d/S98_AB_auto_execution.sh: line 17: /proc/irq/301/smp_affinity: No such file or directory /usr/local/bin/set_unused_gpio_input: line 14: echo: write error: Device or resource busy /usr/local/bin/set_unused_gpio_input: line 15: /sys/class/gpio/gpio161/direction: No such file or directory /usr/local/bin/set_unused_gpio_input: line 14: echo: write error: Device or resource busy /usr/local/bin/set_unused_gpio_input: line 15: /sys/class/gpio/gpio187/direction: No such file or directory INIT: Entering runlevel: 5 Configuring network interfaces... [ 10.572900] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready udhcpc (v1.22.1) started Sending discover... Sending discover... Sending discover... No lease, forking to background done. Starting system message bus: dbus. UIM SYSFS Node Not Found Starting telnet daemon. Starting tiipclad daemon GateMP support enabled on host Opened log file: lad.txt numProcessors = 5 id = 0 baseId = 0 Spawned daemon: /usr/bin/lad_dra7xx . Starting rpcbind daemon...done. creating NFS state directory: done starting statd: done NFS daemon support not enabled in kernel Starting syslogd/klogd: done Starting thttpd. Enabling thermal zones... Stopping Bootlog daemon: bootlogd. root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# ls -al /dev/video1 crw-rw---- 1 root video 81, 1 Jan 1 1970 /dev/video1 root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# ls -al /dev/video* crw-rw---- 1 root video 81, 0 Jan 1 1970 /dev/video0 crw-rw---- 1 root video 81, 1 Jan 1 1970 /dev/video1 crw-rw---- 1 root video 81, 3 Jan 1 1970 /dev/video10 crw-rw---- 1 root video 81, 2 Jan 1 1970 /dev/video11 root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# sh debug_dss_clockdumps.sh =====================DSS clock script=================== Dumps internal clocks and muxes of DSS CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002AF video1 PLL : Disabled video2 PLL : Disabled HDMI PLL : Disabled DSI1_A_CLK mux : DPLL HDMI DSI1_B_CLK mux : DPLL video2 DSI1_C_CLK mux : DPLL Video2 DSS_CTRL (0x58000040) = 0x00000000 2: LCD1 clk switch : DSS clk 3: LCD2 clk switch : DSS clk 10: LCD3 clk switch : DSS clk 1: func clk switch : DSS clk 13: DPI1 output : HDMI ======================================================== Clock O/P of MUXes DSI1_A_CLK : 0 DSI1_B_CLK : 0 DSI1_C_CLK : 0 2: LCD1 clk : 69000000 3: LCD2 clk : 69000000 10: LCD3 clk : 69000000 1: func clk : 69000000 LCD1 logic clk(/ 1 ) : 69000000 pix clk(/ 2 ) : 34500000 LCD2 logic clk(/ 4 ) : 17250000 pix clk(/ 1 ) : 17250000 LCD3 logic clk(/ 1 ) : 69000000 pix clk(/ 1 ) : 69000000 root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# [ 59.347201] random: nonblocking pool is initialized root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# root@wnc-j6:~# gst-launch-1.0 v4l2src device=/dev/video1 num-buffers=1 ! jpegenc ! filesink location=./JPEG_FILE Setting pipeline to PAUSED ... Pipeline is live and does not need PREROLL ... Setting pipeline to PLAYING ...[ 68.794781] 491, r3003 = 17 , r3004 = 23 New clock: GstSystemClock [ 68.802976] ov1063x 4-0037: r3003 = 17 , r3004 = 23 [ 68.810333] 574, width x height = 720 x 480 [ 68.814834] ov1063x 4-0037: width x height = 720 x 480 [ 68.819996] 590, hts x vts = 1083 x 530 [ 68.825137] ov1063x 4-0037: hts x vts = 1083 x 530
DTS file:
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* Based on "omap4.dtsi"
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/dra.h>
#include "skeleton.dtsi"
#define MAX_SOURCES 400
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "ti,dra7xx";
interrupt-parent = <&crossbar_mpu>;
aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
i2c3 = &i2c4;
i2c4 = &i2c5;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
serial5 = &uart6;
serial6 = &uart7;
serial7 = &uart8;
serial8 = &uart9;
serial9 = &uart10;
ethernet0 = &cpsw_emac0;
ethernet1 = &cpsw_emac1;
d_can0 = &dcan1;
d_can1 = &dcan2;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
};
gic: interrupt-controller@48211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0 0x48211000 0x0 0x1000>,
<0x0 0x48212000 0x0 0x1000>,
<0x0 0x48214000 0x0 0x2000>,
<0x0 0x48216000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-parent = <&gic>;
};
wakeupgen: interrupt-controller@48281000 {
compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0 0x48281000 0x0 0x1000>;
interrupt-parent = <&gic>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-opp-domain = <&oppdm_mpu>;
ti,syscon-efuse = <&scm_wkup 0x20c 0xf80000 19>;
ti,syscon-rev = <&scm_wkup 0x204>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
/* cooling options */
cooling-min-level = <0>;
cooling-max-level = <2>;
#cooling-cells = <2>; /* min followed by max */
};
};
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp_nom@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1060000 850000 1150000>;
opp-supported-hw = <0xFF 0x01>;
opp-suspend;
};
opp_od@1176000000 {
opp-hz = /bits/ 64 <1176000000>;
opp-microvolt = <1160000 885000 1160000>;
opp-supported-hw = <0xFF 0x02>;
};
opp_high@1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1210000 950000 1250000>;
opp-supported-hw = <0xFF 0x04>;
};
};
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap5-mpu";
ti,hwmods = "mpu";
};
};
/*
* XXX: Use a flat representation of the SOC interconnect.
* The real OMAP interconnect network is quite complex.
* Since it will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy.
*/
ocp {
compatible = "ti,dra7-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0xc0000000>;
ti,hwmods = "l3_main_1", "l3_main_2";
reg = <0x0 0x44000000 0x0 0x1000000>,
<0x0 0x45000000 0x0 0x1000>;
interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
l4_cfg: l4@4a000000 {
compatible = "ti,dra7-l4-cfg", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a000000 0x22c000>;
scm: scm@2000 {
compatible = "ti,dra7-scm-core", "simple-bus";
reg = <0x2000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x2000>;
scm_conf: scm_conf@0 {
compatible = "syscon", "simple-bus";
reg = <0x0 0x1400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x1400>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-dra7", "ti,pbias-omap";
reg = <0xe00 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap5 {
regulator-name = "pbias_mmc_omap5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
scm_conf_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
dra7_pmx_core: pinmux@1400 {
compatible = "ti,dra7-padconf",
"pinctrl-single";
reg = <0x1400 0x0468>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x3fffffff>;
};
scm_conf1: scm_conf@1c04 {
compatible = "syscon";
reg = <0x1c04 0x0020>;
};
scm_conf_pcie: scm_conf@1c24 {
compatible = "syscon";
reg = <0x1c24 0x0024>;
};
sdma_xbar: dma-router@b78 {
compatible = "ti,dra7-dma-crossbar";
reg = <0xb78 0xfc>;
#dma-cells = <1>;
dma-requests = <205>;
ti,dma-safe-map = <0>;
dma-masters = <&sdma>;
};
edma_xbar: dma-router@c78 {
compatible = "ti,dra7-dma-crossbar";
reg = <0xc78 0x7c>;
#dma-cells = <2>;
dma-requests = <204>;
ti,dma-safe-map = <0>;
dma-masters = <&edma>;
};
};
cm_core_aon: cm_core_aon@5000 {
compatible = "ti,dra7-cm-core-aon";
reg = <0x5000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_aon_clockdomains: clockdomains {
};
};
cm_core: cm_core@8000 {
compatible = "ti,dra7-cm-core";
reg = <0x8000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_clockdomains: clockdomains {
};
};
};
l4_wkup: l4@4ae00000 {
compatible = "ti,dra7-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4ae00000 0x3f000>;
counter32k: counter@4000 {
compatible = "ti,omap-counter32k";
reg = <0x4000 0x40>;
ti,hwmods = "counter_32k";
};
prm: prm@6000 {
compatible = "ti,dra7-prm";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
scm_wkup: scm_conf@c000 {
compatible = "syscon";
reg = <0xc000 0x1000>;
};
};
axi@0 {
compatible = "simple-bus";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x51000000 0x51000000 0x3000
0x0 0x20000000 0x10000000>;
pcie1: pcie@51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
interrupts = <0 232 0x4>, <0 233 0x4>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
#interrupt-cells = <1>;
num-lanes = <1>;
linux,pci-domain = <0>;
ti,hwmods = "pcie1";
phys = <&pcie1_phy>;
phy-names = "pcie-phy0";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 1>,
<0 0 0 2 &pcie1_intc 2>,
<0 0 0 3 &pcie1_intc 3>,
<0 0 0 4 &pcie1_intc 4>;
pcie1_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
axi@1 {
compatible = "simple-bus";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x51800000 0x51800000 0x3000
0x0 0x30000000 0x10000000>;
status = "disabled";
pcie@51800000 {
compatible = "ti,dra7-pcie";
reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
interrupts = <0 355 0x4>, <0 356 0x4>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x30013000 0x13000 0 0xffed000>;
#interrupt-cells = <1>;
num-lanes = <1>;
linux,pci-domain = <1>;
ti,hwmods = "pcie2";
phys = <&pcie2_phy>;
phy-names = "pcie-phy0";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2_intc 1>,
<0 0 0 2 &pcie2_intc 2>,
<0 0 0 3 &pcie2_intc 3>,
<0 0 0 4 &pcie2_intc 4>;
pcie2_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
ocmcram1: ocmcram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x80000>;
ranges = <0x0 0x40300000 0x80000>;
#address-cells = <1>;
#size-cells = <1>;
/*
* This is a placeholder for an optional reserved
* region for use by secure software. The size
* of this region is not known until runtime so it
* is set as zero to either be updated to reserve
* space or left unchanged to leave all SRAM for use.
* On HS parts that that require the reserved region
* either the bootloader can update the size to
* the required amount or the node can be overriden
* from the board dts file for the secure platform.
*/
sram-hs@0 {
compatible = "ti,secure-ram";
reg = <0x0 0x0>;
};
};
/*
* NOTE: ocmcram2 and ocmcram3 are not available on all
* DRA7xx and AM57xx variants. Confirm availability in
* the data manual for the exact part number in use
* before enabling these nodes in the board dts file.
*/
ocmcram2: ocmcram@40400000 {
status = "disabled";
compatible = "mmio-sram";
reg = <0x40400000 0x100000>;
ranges = <0x0 0x40400000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
};
ocmcram3: ocmcram@40500000 {
status = "disabled";
compatible = "mmio-sram";
reg = <0x40500000 0x100000>;
ranges = <0x0 0x40500000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
};
bandgap: bandgap@4a0021e0 {
reg = <0x4a0021e0 0xc
0x4a00232c 0xc
0x4a002380 0x2c
0x4a0023C0 0x3c
0x4a002564 0x8
0x4a002574 0x50>;
compatible = "ti,dra752-bandgap";
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <1>;
};
dsp1_system: dsp_system@40d00000 {
compatible = "syscon";
reg = <0x40d00000 0x100>;
};
dra7_iodelay_core: padconf@4844a000 {
compatible = "ti,dra7-iodelay";
reg = <0x4844a000 0x0d1c>;
#address-cells = <1>;
#size-cells = <0>;
};
sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <32>;
dma-requests = <127>;
};
edma: edma@43300000 {
compatible = "ti,edma3-tpcc";
ti,hwmods = "tpcc";
reg = <0x43300000 0x100000>;
reg-names = "edma3_cc";
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_ccint", "emda3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
/*
* memcpy is disabled, can be enabled with:
* ti,edma-memcpy-channels = <20 21>;
* for example. Note that these channels need to be
* masked in the xbar as well.
*/
};
edma_tptc0: tptc@43400000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc0";
reg = <0x43400000 0x100000>;
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
edma_tptc1: tptc@43500000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc1";
reg = <0x43500000 0x100000>;
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
gpio1: gpio@4ae10000 {
compatible = "ti,omap4-gpio";
reg = <0x4ae10000 0x200>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio1";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@48055000 {
compatible = "ti,omap4-gpio";
reg = <0x48055000 0x200>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio2";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@48057000 {
compatible = "ti,omap4-gpio";
reg = <0x48057000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio3";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@48059000 {
compatible = "ti,omap4-gpio";
reg = <0x48059000 0x200>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio4";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@4805b000 {
compatible = "ti,omap4-gpio";
reg = <0x4805b000 0x200>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio5";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@4805d000 {
compatible = "ti,omap4-gpio";
reg = <0x4805d000 0x200>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio6";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio7: gpio@48051000 {
compatible = "ti,omap4-gpio";
reg = <0x48051000 0x200>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio7";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio8: gpio@48053000 {
compatible = "ti,omap4-gpio";
reg = <0x48053000 0x200>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio8";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
uart1: serial@4806a000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806a000 0x100>;
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&edma_xbar 49 0>, <&edma_xbar 50 0>;
dma-names = "tx", "rx";
};
uart2: serial@4806c000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806c000 0x100>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&edma_xbar 51 0>, <&edma_xbar 52 0>;
dma-names = "tx", "rx";
};
uart3: serial@48020000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48020000 0x100>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&edma_xbar 53 0>, <&edma_xbar 54 0>;
dma-names = "tx", "rx";
};
uart4: serial@4806e000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806e000 0x100>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&edma_xbar 55 0>, <&edma_xbar 56 0>;
dma-names = "tx", "rx";
};
uart5: serial@48066000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48066000 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&edma_xbar 63 0>, <&edma_xbar 64 0>;
dma-names = "tx", "rx";
};
uart6: serial@48068000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48068000 0x100>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&edma_xbar 79 0>, <&edma_xbar 80 0>;
dma-names = "tx", "rx";
};
uart7: serial@48420000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48420000 0x100>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart7";
clock-frequency = <48000000>;
status = "disabled";
};
uart8: serial@48422000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48422000 0x100>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart8";
clock-frequency = <48000000>;
status = "disabled";
};
uart9: serial@48424000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48424000 0x100>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart9";
clock-frequency = <48000000>;
status = "disabled";
};
uart10: serial@4ae2b000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4ae2b000 0x100>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart10";
clock-frequency = <48000000>;
status = "disabled";
};
mailbox1: mailbox@4a0f4000 {
compatible = "ti,omap4-mailbox";
reg = <0x4a0f4000 0x200>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox1";
#mbox-cells = <1>;
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
status = "disabled";
};
mailbox2: mailbox@4883a000 {
compatible = "ti,omap4-mailbox";
reg = <0x4883a000 0x200>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox2";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox3: mailbox@4883c000 {
compatible = "ti,omap4-mailbox";
reg = <0x4883c000 0x200>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox3";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox4: mailbox@4883e000 {
compatible = "ti,omap4-mailbox";
reg = <0x4883e000 0x200>;
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox4";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox5: mailbox@48840000 {
compatible = "ti,omap4-mailbox";
reg = <0x48840000 0x200>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox5";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox6: mailbox@48842000 {
compatible = "ti,omap4-mailbox";
reg = <0x48842000 0x200>;
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox6";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox7: mailbox@48844000 {
compatible = "ti,omap4-mailbox";
reg = <0x48844000 0x200>;
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox7";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox8: mailbox@48846000 {
compatible = "ti,omap4-mailbox";
reg = <0x48846000 0x200>;
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox8";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox9: mailbox@4885e000 {
compatible = "ti,omap4-mailbox";
reg = <0x4885e000 0x200>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox9";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox10: mailbox@48860000 {
compatible = "ti,omap4-mailbox";
reg = <0x48860000 0x200>;
interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox10";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox11: mailbox@48862000 {
compatible = "ti,omap4-mailbox";
reg = <0x48862000 0x200>;
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox11";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox12: mailbox@48864000 {
compatible = "ti,omap4-mailbox";
reg = <0x48864000 0x200>;
interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox12";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox13: mailbox@48802000 {
compatible = "ti,omap4-mailbox";
reg = <0x48802000 0x200>;
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox13";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
timer1: timer@4ae18000 {
compatible = "ti,omap5430-timer";
reg = <0x4ae18000 0x80>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
};
timer2: timer@48032000 {
compatible = "ti,omap5430-timer";
reg = <0x48032000 0x80>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer2";
};
timer3: timer@48034000 {
compatible = "ti,omap5430-timer";
reg = <0x48034000 0x80>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer3";
};
timer4: timer@48036000 {
compatible = "ti,omap5430-timer";
reg = <0x48036000 0x80>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer4";
};
timer5: timer@48820000 {
compatible = "ti,omap5430-timer";
reg = <0x48820000 0x80>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer5";
};
timer6: timer@48822000 {
compatible = "ti,omap5430-timer";
reg = <0x48822000 0x80>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer6";
};
timer7: timer@48824000 {
compatible = "ti,omap5430-timer";
reg = <0x48824000 0x80>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer7";
};
timer8: timer@48826000 {
compatible = "ti,omap5430-timer";
reg = <0x48826000 0x80>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer8";
};
timer9: timer@4803e000 {
compatible = "ti,omap5430-timer";
reg = <0x4803e000 0x80>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer9";
};
timer10: timer@48086000 {
compatible = "ti,omap5430-timer";
reg = <0x48086000 0x80>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer10";
};
timer11: timer@48088000 {
compatible = "ti,omap5430-timer";
reg = <0x48088000 0x80>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer11";
};
timer12: timer@4ae20000 {
compatible = "ti,omap5430-timer";
reg = <0x4ae20000 0x80>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer12";
ti,timer-alwon;
ti,timer-secure;
};
timer13: timer@48828000 {
compatible = "ti,omap5430-timer";
reg = <0x48828000 0x80>;
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer13";
status = "disabled";
};
timer14: timer@4882a000 {
compatible = "ti,omap5430-timer";
reg = <0x4882a000 0x80>;
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer14";
status = "disabled";
};
timer15: timer@4882c000 {
compatible = "ti,omap5430-timer";
reg = <0x4882c000 0x80>;
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer15";
status = "disabled";
};
timer16: timer@4882e000 {
compatible = "ti,omap5430-timer";
reg = <0x4882e000 0x80>;
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer16";
status = "disabled";
};
wdt2: wdt@4ae14000 {
compatible = "ti,omap3-wdt";
reg = <0x4ae14000 0x80>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "wd_timer2";
};
hwspinlock: spinlock@4a0f6000 {
compatible = "ti,omap4-hwspinlock";
reg = <0x4a0f6000 0x1000>;
ti,hwmods = "spinlock";
#hwlock-cells = <1>;
};
dmm@4e000000 {
compatible = "ti,omap5-dmm";
reg = <0x4e000000 0x800>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dmm";
};
ipu1: ipu@58820000 {
compatible = "ti,dra7-ipu";
reg = <0x58820000 0x10000>;
reg-names = "l2ram";
ti,hwmods = "ipu1";
iommus = <&mmu_ipu1>;
ti,rproc-standby-info = <0x4a005520>;
status = "disabled";
};
ipu2: ipu@55020000 {
compatible = "ti,dra7-ipu";
reg = <0x55020000 0x10000>;
reg-names = "l2ram";
ti,hwmods = "ipu2";
iommus = <&mmu_ipu2>;
ti,rproc-standby-info = <0x4a008920>;
status = "disabled";
};
dsp1: dsp@40800000 {
compatible = "ti,dra7-dsp";
reg = <0x40800000 0x48000>,
<0x40e00000 0x8000>,
<0x40f00000 0x8000>;
reg-names = "l2ram", "l1pram", "l1dram";
ti,hwmods = "dsp1";
syscon-bootreg = <&scm_conf 0x55c>;
iommus = <&mmu0_dsp1>, <&mmu1_dsp1>;
ti,rproc-standby-info = <0x4a005420>;
status = "disabled";
};
gpu: gpu@56000000 {
compatible = "ti,dra7-sgx544", "img,sgx544";
reg = <0x56000000 0x10000>;
reg-names = "gpu_ocp_base";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpu";
clocks = <&l3_iclk_div>, <&gpu_core_gclk_mux>,
<&gpu_hyd_gclk_mux>;
clock-names = "iclk", "fclk1", "fclk2";
};
bb2d: bb2d@59000000 {
compatible = "ti,dra7-bb2d";
reg = <0x59000000 0x0700>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "bb2d";
clocks = <&dpll_core_h24x2_ck>;
clock-names = "fck";
};
i2c1: i2c@48070000 {
compatible = "ti,omap4-i2c";
reg = <0x48070000 0x100>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
status = "disabled";
};
i2c2: i2c@48072000 {
compatible = "ti,omap4-i2c";
reg = <0x48072000 0x100>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
status = "disabled";
};
i2c3: i2c@48060000 {
compatible = "ti,omap4-i2c";
reg = <0x48060000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
status = "disabled";
};
i2c4: i2c@4807a000 {
compatible = "ti,omap4-i2c";
reg = <0x4807a000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c4";
status = "disabled";
};
i2c5: i2c@4807c000 {
compatible = "ti,omap4-i2c";
reg = <0x4807c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c5";
status = "disabled";
};
mmc1: mmc@4809c000 {
compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
reg = <0x4809c000 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
dma-names = "tx", "rx";
status = "disabled";
pbias-supply = <&pbias_mmc_reg>;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-ddr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
};
mmc2: mmc@480b4000 {
compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
reg = <0x480b4000 0x400>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
dma-names = "tx", "rx";
status = "disabled";
#if 0
sd-uhs-sdr25;
sd-uhs-sdr12;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
#endif
};
mmc3: mmc@480ad000 {
compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
reg = <0x480ad000 0x400>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc3";
ti,needs-special-reset;
dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
dma-names = "tx", "rx";
status = "disabled";
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
};
mmc4: mmc@480d1000 {
compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
reg = <0x480d1000 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc4";
ti,needs-special-reset;
dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
dma-names = "tx", "rx";
status = "disabled";
#if 0
sd-uhs-sdr12;
sd-uhs-sdr25;
#endif
};
mmu0_dsp1: mmu@40d01000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x40d01000 0x100>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu0_dsp1";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp1_system 0x0>;
status = "disabled";
};
mmu1_dsp1: mmu@40d02000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x40d02000 0x100>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu1_dsp1";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp1_system 0x1>;
status = "disabled";
};
mmu_ipu1: mmu@58882000 {
compatible = "ti,dra7-iommu";
reg = <0x58882000 0x100>;
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_ipu1";
#iommu-cells = <0>;
ti,iommu-bus-err-back;
status = "disabled";
};
mmu_ipu2: mmu@55082000 {
compatible = "ti,dra7-iommu";
reg = <0x55082000 0x100>;
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_ipu2";
#iommu-cells = <0>;
ti,iommu-bus-err-back;
status = "disabled";
};
pruss1: pruss@4b200000 {
compatible = "ti,am5728-pruss";
ti,hwmods = "pruss1";
reg = <0x4b200000 0x2000>,
<0x4b202000 0x2000>,
<0x4b210000 0x8000>,
<0x4b226000 0x2000>,
<0x4b22e000 0x31c>,
<0x4b232000 0x58>;
reg-names = "dram0", "dram1", "shrdram2", "cfg",
"iep", "mii_rt";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
pruss1_intc: intc@4b220000 {
compatible = "ti,am5728-pruss-intc";
reg = <0x4b220000 0x2000>;
reg-names = "intc";
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host2", "host3", "host4",
"host5", "host6", "host7",
"host8", "host9";
interrupt-controller;
#interrupt-cells = <1>;
};
pru1_0: pru0@4b234000 {
compatible = "ti,am5728-pru";
reg = <0x4b234000 0x3000>,
<0x4b222000 0x400>,
<0x4b222400 0x100>;
reg-names = "iram", "control", "debug";
status = "disabled";
};
pru1_1: pru1@4b238000 {
compatible = "ti,am5728-pru";
reg = <0x4b238000 0x3000>,
<0x4b224000 0x400>,
<0x4b224400 0x100>;
reg-names = "iram", "control", "debug";
status = "disabled";
};
pruss1_mdio: mdio@4b232400 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&dpll_gmac_h13x2_ck>;
clock-names = "fck";
bus_freq = <1000000>;
reg = <0x4b232400 0x90>;
status = "disabled";
};
};
pruss2: pruss@4b280000 {
compatible = "ti,am5728-pruss";
ti,hwmods = "pruss2";
reg = <0x4b280000 0x2000>,
<0x4b282000 0x2000>,
<0x4b290000 0x8000>,
<0x4b2a6000 0x2000>,
<0x4b2ae000 0x31c>,
<0x4b2b2000 0x58>;
reg-names = "dram0", "dram1", "shrdram2", "cfg",
"iep", "mii_rt";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
pruss2_intc: intc@4b2a0000 {
compatible = "ti,am5728-pruss-intc";
reg = <0x4b2a0000 0x2000>;
reg-names = "intc";
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host2", "host3", "host4",
"host5", "host6", "host7",
"host8", "host9";
interrupt-controller;
#interrupt-cells = <1>;
};
pru2_0: pru0@4b2b4000 {
compatible = "ti,am5728-pru";
reg = <0x4b2b4000 0x3000>,
<0x4b2a2000 0x400>,
<0x4b2a2400 0x100>;
reg-names = "iram", "control", "debug";
status = "disabled";
};
pru2_1: pru1@4b2b8000 {
compatible = "ti,am5728-pru";
reg = <0x4b2b8000 0x3000>,
<0x4b2a4000 0x400>,
<0x4b2a4400 0x100>;
reg-names = "iram", "control", "debug";
status = "disabled";
};
pruss2_mdio: mdio@4b2b2400 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&dpll_gmac_h13x2_ck>;
clock-names = "fck";
bus_freq = <1000000>;
reg = <0x4b2b2400 0x90>;
status = "disabled";
};
};
abb_mpu: regulator-abb-mpu {
compatible = "ti,abb-v3";
regulator-name = "abb_mpu";
#address-cells = <0>;
#size-cells = <0>;
clocks = <&sys_clkin1>;
ti,settling-time = <50>;
ti,clock-cycles = <16>;
reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
<0x4ae06014 0x4>, <0x4a003b20 0xc>,
<0x4ae0c158 0x4>;
reg-names = "setup-address", "control-address",
"int-address", "efuse-address",
"ldo-address";
ti,tranxdone-status-mask = <0x80>;
/* LDOVBBMPU_FBB_MUX_CTRL */
ti,ldovbb-override-mask = <0x400>;
/* LDOVBBMPU_FBB_VSET_OUT */
ti,ldovbb-vset-mask = <0x1F>;
/*
* NOTE: only FBB mode used but actual vset will
* determine final biasing
*/
ti,abb_info = <
/*uV ABB efuse rbb_m fbb_m vset_m*/
1060000 0 0x0 0 0x02000000 0x01F00000
1160000 0 0x4 0 0x02000000 0x01F00000
1210000 0 0x8 0 0x02000000 0x01F00000
>;
};
abb_ivahd: regulator-abb-ivahd {
compatible = "ti,abb-v3";
regulator-name = "abb_ivahd";
#address-cells = <0>;
#size-cells = <0>;
clocks = <&sys_clkin1>;
ti,settling-time = <50>;
ti,clock-cycles = <16>;
reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
<0x4ae06010 0x4>, <0x4a0025cc 0xc>,
<0x4a002470 0x4>;
reg-names = "setup-address", "control-address",
"int-address", "efuse-address",
"ldo-address";
ti,tranxdone-status-mask = <0x40000000>;
/* LDOVBBIVA_FBB_MUX_CTRL */
ti,ldovbb-override-mask = <0x400>;
/* LDOVBBIVA_FBB_VSET_OUT */
ti,ldovbb-vset-mask = <0x1F>;
/*
* NOTE: only FBB mode used but actual vset will
* determine final biasing
*/
ti,abb_info = <
/*uV ABB efuse rbb_m fbb_m vset_m*/
1055000 0 0x0 0 0x02000000 0x01F00000
1150000 0 0x4 0 0x02000000 0x01F00000
1250000 0 0x8 0 0x02000000 0x01F00000
>;
};
abb_dspeve: regulator-abb-dspeve {
compatible = "ti,abb-v3";
regulator-name = "abb_dspeve";
#address-cells = <0>;
#size-cells = <0>;
clocks = <&sys_clkin1>;
ti,settling-time = <50>;
ti,clock-cycles = <16>;
reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
<0x4ae06010 0x4>, <0x4a0025e0 0xc>,
<0x4a00246c 0x4>;
reg-names = "setup-address", "control-address",
"int-address", "efuse-address",
"ldo-address";
ti,tranxdone-status-mask = <0x20000000>;
/* LDOVBBDSPEVE_FBB_MUX_CTRL */
ti,ldovbb-override-mask = <0x400>;
/* LDOVBBDSPEVE_FBB_VSET_OUT */
ti,ldovbb-vset-mask = <0x1F>;
/*
* NOTE: only FBB mode used but actual vset will
* determine final biasing
*/
ti,abb_info = <
/*uV ABB efuse rbb_m fbb_m vset_m*/
1055000 0 0x0 0 0x02000000 0x01F00000
1150000 0 0x4 0 0x02000000 0x01F00000
1250000 0 0x8 0 0x02000000 0x01F00000
>;
};
abb_gpu: regulator-abb-gpu {
compatible = "ti,abb-v3";
regulator-name = "abb_gpu";
#address-cells = <0>;
#size-cells = <0>;
clocks = <&sys_clkin1>;
ti,settling-time = <50>;
ti,clock-cycles = <16>;
reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
<0x4ae06010 0x4>, <0x4a003b08 0xc>,
<0x4ae0c154 0x4>;
reg-names = "setup-address", "control-address",
"int-address", "efuse-address",
"ldo-address";
ti,tranxdone-status-mask = <0x10000000>;
/* LDOVBBGPU_FBB_MUX_CTRL */
ti,ldovbb-override-mask = <0x400>;
/* LDOVBBGPU_FBB_VSET_OUT */
ti,ldovbb-vset-mask = <0x1F>;
/*
* NOTE: only FBB mode used but actual vset will
* determine final biasing
*/
ti,abb_info = <
/*uV ABB efuse rbb_m fbb_m vset_m*/
1090000 0 0x0 0 0x02000000 0x01F00000
1210000 0 0x4 0 0x02000000 0x01F00000
1280000 0 0x8 0 0x02000000 0x01F00000
>;
};
oppdm_mpu: oppdm@4a003b20 {
compatible = "ti,omap5-oppdm";
#oppdm-cells = <0>;
vbb-supply = <&abb_mpu>;
reg = <0x4a003b20 0xc>;
ti,efuse-settings = <
/* uV offset */
1060000 0x0
1160000 0x4
1210000 0x8
>;
ti,absolute-max-voltage-uv = <1500000>;
};
oppdm_ivahd: oppdm@4a0025cc {
compatible = "ti,omap5-oppdm";
#oppdm-cells = <0>;
vbb-supply = <&abb_ivahd>;
reg = <0x4a0025cc 0xc>;
ti,efuse-settings = <
/* uV offset */
1055000 0x0
1150000 0x4
1250000 0x8
>;
ti,absolute-max-voltage-uv = <1500000>;
};
oppdm_dspeve: oppdm@4a0025e0 {
compatible = "ti,omap5-oppdm";
#oppdm-cells = <0>;
vbb-supply = <&abb_dspeve>;
reg = <0x4a0025e0 0xc>;
ti,efuse-settings = <
/* uV offset */
1055000 0x0
1150000 0x4
1250000 0x8
>;
ti,absolute-max-voltage-uv = <1500000>;
};
oppdm_gpu: oppdm@4a003b08 {
compatible = "ti,omap5-oppdm";
#oppdm-cells = <0>;
vbb-supply = <&abb_gpu>;
reg = <0x4a003b08 0xc>;
ti,efuse-settings = <
/* uV offset */
1090000 0x0
1210000 0x4
1280000 0x8
>;
ti,absolute-max-voltage-uv = <1500000>;
};
oppdm_core: oppdm@4a0025f4 {
compatible = "ti,omap5-core-oppdm";
#oppdm-cells = <0>;
reg = <0x4a0025f4 0x4>;
ti,efuse-settings = <
/* uV offset */
1090000 0x0
>;
ti,absolute-max-voltage-uv = <1500000>;
};
mcspi1: spi@48098000 {
compatible = "ti,omap4-mcspi";
reg = <0x48098000 0x200>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi1";
ti,spi-num-cs = <4>;
dmas = <&sdma_xbar 35>,
<&sdma_xbar 36>,
<&sdma_xbar 37>,
<&sdma_xbar 38>,
<&sdma_xbar 39>,
<&sdma_xbar 40>,
<&sdma_xbar 41>,
<&sdma_xbar 42>;
dma-names = "tx0", "rx0", "tx1", "rx1",
"tx2", "rx2", "tx3", "rx3";
status = "disabled";
};
mcspi2: spi@4809a000 {
compatible = "ti,omap4-mcspi";
reg = <0x4809a000 0x200>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi2";
ti,spi-num-cs = <2>;
dmas = <&sdma_xbar 43>,
<&sdma_xbar 44>,
<&sdma_xbar 45>,
<&sdma_xbar 46>;
dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled";
};
mcspi3: spi@480b8000 {
compatible = "ti,omap4-mcspi";
reg = <0x480b8000 0x200>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi3";
ti,spi-num-cs = <2>;
dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
dma-names = "tx0", "rx0";
status = "disabled";
};
mcspi4: spi@480ba000 {
compatible = "ti,omap4-mcspi";
reg = <0x480ba000 0x200>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi4";
ti,spi-num-cs = <1>;
dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
dma-names = "tx0", "rx0";
status = "disabled";
};
qspi: qspi@4b300000 {
compatible = "ti,dra7xxx-qspi";
reg = <0x4b300000 0x100>,
<0x5c000000 0x4000000>;
reg-names = "qspi_base", "qspi_mmap";
syscon-chipselects = <&scm_conf 0x558>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
clocks = <&qspi_gfclk_div>;
clock-names = "fck";
num-cs = <4>;
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
/* OCP2SCP3 */
ocp2scp@4a090000 {
compatible = "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x4a090000 0x20>;
ti,hwmods = "ocp2scp3";
sata_phy: phy@4A096000 {
compatible = "ti,phy-pipe3-sata";
reg = <0x4A096000 0x80>, /* phy_rx */
<0x4A096400 0x64>, /* phy_tx */
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
syscon-phy-power = <&scm_conf 0x374>;
clocks = <&sys_clkin1>, <&sata_ref_clk>;
clock-names = "sysclk", "refclk";
syscon-pllreset = <&scm_conf 0x3fc>;
#phy-cells = <0>;
};
pcie1_phy: pciephy@4a094000 {
compatible = "ti,phy-pipe3-pcie";
reg = <0x4a094000 0x80>, /* phy_rx */
<0x4a094400 0x64>; /* phy_tx */
reg-names = "phy_rx", "phy_tx";
syscon-phy-power = <&scm_conf_pcie 0x1c>;
syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy1_32khz>,
<&optfclk_pciephy1_clk>,
<&optfclk_pciephy1_div_clk>,
<&optfclk_pciephy_div>,
<&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
"wkupclk", "refclk",
"div-clk", "phy-div", "sysclk";
#phy-cells = <0>;
};
pcie2_phy: pciephy@4a095000 {
compatible = "ti,phy-pipe3-pcie";
reg = <0x4a095000 0x80>, /* phy_rx */
<0x4a095400 0x64>; /* phy_tx */
reg-names = "phy_rx", "phy_tx";
syscon-phy-power = <&scm_conf_pcie 0x20>;
syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy2_32khz>,
<&optfclk_pciephy2_clk>,
<&optfclk_pciephy2_div_clk>,
<&optfclk_pciephy_div>,
<&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
"wkupclk", "refclk",
"div-clk", "phy-div", "sysclk";
#phy-cells = <0>;
status = "disabled";
};
};
sata: sata@4a141100 {
compatible = "snps,dwc-ahci";
reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
phys = <&sata_phy>;
phy-names = "sata-phy";
clocks = <&sata_ref_clk>;
ti,hwmods = "sata";
};
rtc: rtc@48838000 {
compatible = "ti,am3352-rtc";
reg = <0x48838000 0x100>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "rtcss";
clocks = <&sys_32k_ck>;
};
/* OCP2SCP1 */
ocp2scp@4a080000 {
compatible = "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x4a080000 0x20>;
ti,hwmods = "ocp2scp1";
usb2_phy1: phy@4a084000 {
compatible = "ti,dra7x-usb2", "ti,omap-usb2";
reg = <0x4a084000 0x400>;
syscon-phy-power = <&scm_conf 0x300>;
clocks = <&usb_phy1_always_on_clk32k>,
<&usb_otg_ss1_refclk960m>;
clock-names = "wkupclk",
"refclk";
#phy-cells = <0>;
};
usb2_phy2: phy@4a085000 {
compatible = "ti,dra7x-usb2-phy2",
"ti,omap-usb2";
reg = <0x4a085000 0x400>;
syscon-phy-power = <&scm_conf 0xe74>;
clocks = <&usb_phy2_always_on_clk32k>,
<&usb_otg_ss2_refclk960m>;
clock-names = "wkupclk",
"refclk";
#phy-cells = <0>;
};
usb3_phy1: phy@4a084400 {
compatible = "ti,omap-usb3";
reg = <0x4a084400 0x80>,
<0x4a084800 0x64>,
<0x4a084c00 0x40>;
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
syscon-phy-power = <&scm_conf 0x370>;
clocks = <&usb_phy3_always_on_clk32k>,
<&sys_clkin1>,
<&usb_otg_ss1_refclk960m>;
clock-names = "wkupclk",
"sysclk",
"refclk";
#phy-cells = <0>;
};
};
omap_dwc3_1: omap_dwc3_1@48880000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss1";
reg = <0x48880000 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
ranges;
usb1: usb@48890000 {
compatible = "snps,dwc3";
reg = <0x48890000 0x17000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral",
"host",
"otg";
phys = <&usb2_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
tx-fifo-resize;
maximum-speed = "super-speed";
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
snps,dis_u2_susphy_quirk;
};
};
omap_dwc3_2: omap_dwc3_2@488c0000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss2";
reg = <0x488c0000 0x10000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
ranges;
usb2: usb@488d0000 {
compatible = "snps,dwc3";
reg = <0x488d0000 0x17000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral",
"host",
"otg";
phys = <&usb2_phy2>;
phy-names = "usb2-phy";
tx-fifo-resize;
maximum-speed = "high-speed";
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
snps,dis_u2_susphy_quirk;
};
};
/* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
omap_dwc3_3: omap_dwc3_3@48900000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss3";
reg = <0x48900000 0x10000>;
interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
ranges;
//status = "disabled";
usb3: usb@48910000 {
compatible = "snps,dwc3";
reg = <0x48910000 0x17000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral",
"host",
"otg";
tx-fifo-resize;
maximum-speed = "high-speed";
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
snps,dis_u2_susphy_quirk;
};
};
elm: elm@48078000 {
compatible = "ti,am3352-elm";
reg = <0x48078000 0xfc0>; /* device IO registers */
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "elm";
status = "disabled";
};
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
reg = <0x50000000 0x37c>; /* device IO registers */
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 4 0>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
atl: atl@4843c000 {
compatible = "ti,dra7-atl";
reg = <0x4843c000 0x3ff>;
ti,hwmods = "atl";
ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
clocks = <&atl_gfclk_mux>;
clock-names = "fck";
status = "disabled";
};
mcasp1: mcasp@48460000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp1";
reg = <0x48460000 0x2000>,
<0x45800000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
dma-names = "tx", "rx";
clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
<&mcasp1_ahclkr_mux>;
clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled";
};
mcasp2: mcasp@48464000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp2";
reg = <0x48464000 0x2000>,
<0x45c00000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
dma-names = "tx", "rx";
clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
<&mcasp2_ahclkr_mux>;
clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled";
};
mcasp3: mcasp@48468000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp3";
reg = <0x48468000 0x2000>,
<0x46000000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
dma-names = "tx", "rx";
clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
mcasp4: mcasp@4846c000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp4";
reg = <0x4846c000 0x2000>,
<0x48436000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
dma-names = "tx", "rx";
clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
mcasp5: mcasp@48470000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp5";
reg = <0x48470000 0x2000>,
<0x4843a000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
dma-names = "tx", "rx";
clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
mcasp6: mcasp@48474000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp6";
reg = <0x48474000 0x2000>,
<0x4844c000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
dma-names = "tx", "rx";
clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
mcasp7: mcasp@48478000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp7";
reg = <0x48478000 0x2000>,
<0x48450000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
dma-names = "tx", "rx";
clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
mcasp8: mcasp@4847c000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp8";
reg = <0x4847c000 0x2000>,
<0x48454000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
dma-names = "tx", "rx";
clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
crossbar_mpu: crossbar@4a002a48 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
interrupt-controller;
interrupt-parent = <&wakeupgen>;
#interrupt-cells = <3>;
ti,max-irqs = <160>;
ti,max-crossbar-sources = <MAX_SOURCES>;
ti,reg-size = <2>;
ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
ti,irqs-skip = <10 133 139 140>;
ti,irqs-safe-map = <0>;
};
mac: ethernet@48484000 {
compatible = "ti,dra7-cpsw","ti,cpsw";
ti,hwmods = "gmac";
clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
reg = <0x48484000 0x1000
0x48485200 0x2E00>;
#address-cells = <1>;
#size-cells = <1>;
/*
* Do not allow gating of cpsw clock as workaround
* for errata i877. Keeping internal clock disabled
* causes the device switching characteristics
* to degrade over time and eventually fail to meet
* the data manual delay time/skew specs.
*/
ti,no-idle;
/*
* rx_thresh_pend
* rx_pend
* tx_pend
* misc_pend
*/
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
ranges;
syscon = <&scm_conf>;
status = "disabled";
davinci_mdio: mdio@48485000 {
compatible = "ti,cpsw-mdio";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
reg = <0x48485000 0x100>;
};
cpsw_emac0: slave@48480200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave@48480300 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
phy_sel: cpsw-phy-sel@4a002554 {
compatible = "ti,dra7xx-cpsw-phy-sel";
reg= <0x4a002554 0x4>;
reg-names = "gmii-sel";
};
};
dcan1: can@481cc000 {
compatible = "ti,dra7-d_can";
ti,hwmods = "dcan1";
reg = <0x4ae3c000 0x2000>;
syscon-raminit = <&scm_conf 0x558 0>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dcan1_sys_clk_mux>;
status = "disabled";
};
dcan2: can@481d0000 {
compatible = "ti,dra7-d_can";
ti,hwmods = "dcan2";
reg = <0x48480000 0x2000>;
syscon-raminit = <&scm_conf 0x558 1>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_clkin1>;
status = "disabled";
};
dss: dss@58000000 {
compatible = "ti,dra7-dss";
/* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
/* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
status = "disabled";
ti,hwmods = "dss_core";
/* CTRL_CORE_DSS_PLL_CONTROL */
syscon-pll-ctrl = <&scm_conf 0x538>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
dispc@58001000 {
compatible = "ti,dra7-dispc";
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
clocks = <&dss_dss_clk>;
clock-names = "fck";
/* CTRL_CORE_SMA_SW_1 */
syscon-pol = <&scm_conf 0x534>;
};
hdmi: encoder@58060000 {
compatible = "ti,dra7-hdmi";
reg = <0x58040000 0x200>,
<0x58040200 0x80>,
<0x58040300 0x80>,
<0x58060000 0x19000>;
reg-names = "wp", "pll", "phy", "core";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_hdmi";
clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
clock-names = "fck", "sys_clk";
dmas = <&sdma_xbar 76>;
dma-names = "audio_tx";
};
};
vpe {
compatible = "ti,vpe";
ti,hwmods = "vpe";
clocks = <&dpll_core_h23x2_ck>;
clock-names = "fck";
reg = <0x489d0000 0x120>,
<0x489d0300 0x20>,
<0x489d0400 0x20>,
<0x489d0500 0x20>,
<0x489d0600 0x3c>,
<0x489d0700 0x80>,
<0x489d5700 0x18>,
<0x489dd000 0x400>;
reg-names = "vpe_top",
"vpe_chr_us0",
"vpe_chr_us1",
"vpe_chr_us2",
"vpe_dei",
"sc",
"csc",
"vpdma";
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
};
vip1: vip@0x48970000 {
compatible = "ti,vip1";
reg = <0x48970000 0x114>,
<0x48975500 0xD8>,
<0x48975700 0x18>,
<0x48975800 0x80>,
<0x48975a00 0xD8>,
<0x48975c00 0x18>,
<0x48975d00 0x80>,
<0x4897d000 0x400>;
reg-names = "vip",
"parser0",
"csc0",
"sc0",
"parser1",
"csc1",
"sc1",
"vpdma";
ti,hwmods = "vip1";
interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
/* CTRL_CORE_SMA_SW_1 */
syscon-pol = <&scm_conf 0x534>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
vin1a: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
};
vin2a: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "disabled";
};
vin1b: port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
};
vin2b: port@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "disabled";
};
};
epwmss0: epwmss@4843e000 {
compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
reg = <0x4843e000 0x30>;
ti,hwmods = "epwmss0";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges;
ehrpwm0: pwm@4843e200 {
compatible = "ti,dra7xx-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x4843e200 0x80>;
clocks = <&ehrpwm0_tbclk>;
clock-names = "tbclk";
status = "disabled";
};
ecap0: ecap@4843e100 {
compatible = "ti,dra7xx-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x4843e100 0x80>;
status = "disabled";
};
};
epwmss1: epwmss@48440000 {
compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
reg = <0x48440000 0x30>;
ti,hwmods = "epwmss1";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges;
ehrpwm1: pwm@48440200 {
compatible = "ti,dra7xx-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48440200 0x80>;
clocks = <&ehrpwm1_tbclk>;
clock-names = "tbclk";
status = "disabled";
};
ecap1: ecap@48440100 {
compatible = "ti,dra7xx-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48440100 0x80>;
status = "disabled";
};
};
epwmss2: epwmss@48442000 {
compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
reg = <0x48442000 0x30>;
ti,hwmods = "epwmss2";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges;
ehrpwm2: pwm@48442200 {
compatible = "ti,dra7xx-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48442200 0x80>;
clocks = <&ehrpwm2_tbclk>;
clock-names = "tbclk";
status = "disabled";
};
ecap2: ecap@48442100 {
compatible = "ti,dra7xx-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48442100 0x80>;
status = "disabled";
};
};
aes1: aes@4b500000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes1";
reg = <0x4b500000 0xa0>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
aes2: aes@4b700000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes2";
reg = <0x4b700000 0xa0>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
des: des@480a5000 {
compatible = "ti,omap4-des";
ti,hwmods = "des";
reg = <0x480a5000 0xa0>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
sham: sham@53100000 {
compatible = "ti,omap5-sham";
ti,hwmods = "sham";
reg = <0x4b101000 0x300>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 119 0>;
dma-names = "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
rng: rng@48090000 {
compatible = "ti,omap4-rng";
ti,hwmods = "rng";
reg = <0x48090000 0x2000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
};
thermal_zones: thermal-zones {
#include "omap4-cpu-thermal.dtsi"
#include "omap5-gpu-thermal.dtsi"
#include "omap5-core-thermal.dtsi"
#include "dra7-dspeve-thermal.dtsi"
#include "dra7-iva-thermal.dtsi"
};
};
&cpu_thermal {
polling-delay = <500>; /* milliseconds */
};
/include/ "dra7xx-clocks.dtsi"
/*
* Device Tree Source for DRA7xx clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&cm_core_aon_clocks {
atl_clkin0_ck: atl_clkin0_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
atl_clkin1_ck: atl_clkin1_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
atl_clkin2_ck: atl_clkin2_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
atl_clkin3_ck: atl_clkin3_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
hdmi_clkin_ck: hdmi_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
mlb_clkin_ck: mlb_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
mlbp_clkin_ck: mlbp_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
pciesref_acs_clk_ck: pciesref_acs_clk_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
ref_clkin0_ck: ref_clkin0_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
ref_clkin1_ck: ref_clkin1_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
ref_clkin2_ck: ref_clkin2_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
ref_clkin3_ck: ref_clkin3_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
rmii_clk_ck: rmii_clk_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
sdvenc_clkin_ck: sdvenc_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
secure_32k_clk_src_ck: secure_32k_clk_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
sys_clk32_crystal_ck: sys_clk32_crystal_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin1>;
clock-mult = <1>;
clock-div = <610>;
};
virt_12000000_ck: virt_12000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <12000000>;
};
virt_13000000_ck: virt_13000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <13000000>;
};
virt_16800000_ck: virt_16800000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <16800000>;
};
virt_19200000_ck: virt_19200000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <19200000>;
};
virt_20000000_ck: virt_20000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
virt_26000000_ck: virt_26000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <26000000>;
};
virt_27000000_ck: virt_27000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <27000000>;
};
virt_38400000_ck: virt_38400000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <38400000>;
};
sys_clkin2: sys_clkin2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <22579200>;
};
usb_otg_clkin_ck: usb_otg_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
video1_clkin_ck: video1_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
video1_m2_clkin_ck: video1_m2_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
video2_clkin_ck: video2_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
video2_m2_clkin_ck: video2_m2_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
dpll_abe_ck: dpll_abe_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
};
dpll_abe_x2_ck: dpll_abe_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_abe_ck>;
};
dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x01f0>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
abe_clk: abe_clk {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
ti,max-div = <4>;
reg = <0x0108>;
ti,index-power-of-two;
};
dpll_abe_m2_ck: dpll_abe_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x01f0>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x01f4>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_byp_mux: dpll_core_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x012c>;
};
dpll_core_ck: dpll_core_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_core_ck>;
};
dpll_core_h12x2_ck: dpll_core_h12x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x013c>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_mpu_ck: dpll_mpu_ck {
#clock-cells = <0>;
compatible = "ti,omap5-mpu-dpll-clock";
clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0170>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
mpu_dclk_div: mpu_dclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_mpu_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_dsp_byp_mux: dpll_dsp_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x0240>;
};
dpll_dsp_ck: dpll_dsp_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
assigned-clocks = <&dpll_dsp_ck>;
assigned-clock-rates = <600000000>;
};
dpll_dsp_m2_ck: dpll_dsp_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0244>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
assigned-clocks = <&dpll_dsp_m2_ck>;
assigned-clock-rates = <600000000>;
};
iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_iva_byp_mux: dpll_iva_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x01ac>;
};
dpll_iva_ck: dpll_iva_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
assigned-clocks = <&dpll_iva_ck>;
assigned-clock-rates = <1165000000>;
};
dpll_iva_m2_ck: dpll_iva_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_iva_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x01b0>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
assigned-clocks = <&dpll_iva_m2_ck>;
assigned-clock-rates = <388333334>;
};
iva_dclk: iva_dclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_iva_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_gpu_byp_mux: dpll_gpu_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x02e4>;
};
dpll_gpu_ck: dpll_gpu_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
assigned-clocks = <&dpll_gpu_ck>;
assigned-clock-rates = <1277000000>;
};
dpll_gpu_m2_ck: dpll_gpu_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x02e8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
assigned-clocks = <&dpll_gpu_m2_ck>;
assigned-clock-rates = <425666667>;
};
dpll_core_m2_ck: dpll_core_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0130>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
core_dpll_out_dclk_div: core_dpll_out_dclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_core_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_ddr_byp_mux: dpll_ddr_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x021c>;
};
dpll_ddr_ck: dpll_ddr_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0220>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_gmac_byp_mux: dpll_gmac_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x02b4>;
};
dpll_gmac_ck: dpll_gmac_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
};
dpll_gmac_m2_ck: dpll_gmac_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x02b8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
video2_dclk_div: video2_dclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&video2_m2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
video1_dclk_div: video1_dclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&video1_m2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
hdmi_dclk_div: hdmi_dclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
per_dpll_hs_clk_div: per_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <3>;
};
eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_eve_byp_mux: dpll_eve_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x0290>;
};
dpll_eve_ck: dpll_eve_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
};
dpll_eve_m2_ck: dpll_eve_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_eve_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0294>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
eve_dclk_div: eve_dclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_eve_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_core_h13x2_ck: dpll_core_h13x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0140>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_h14x2_ck: dpll_core_h14x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0144>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_h22x2_ck: dpll_core_h22x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0154>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_h23x2_ck: dpll_core_h23x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0158>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_h24x2_ck: dpll_core_h24x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x015c>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_ddr_x2_ck: dpll_ddr_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_ddr_ck>;
};
dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0228>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_dsp_x2_ck: dpll_dsp_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_dsp_ck>;
};
dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0248>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
assigned-clocks = <&dpll_dsp_m3x2_ck>;
assigned-clock-rates = <400000000>;
};
dpll_gmac_x2_ck: dpll_gmac_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_gmac_ck>;
};
dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x02c0>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x02c4>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x02c8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x02bc>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
gmii_m_clk_div: gmii_m_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_gmac_h11x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
hdmi_clk2_div: hdmi_clk2_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
hdmi_div_clk: hdmi_div_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
l3_iclk_div: l3_iclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
ti,max-div = <2>;
ti,bit-shift = <4>;
reg = <0x0100>;
clocks = <&dpll_core_h12x2_ck>;
ti,index-power-of-two;
};
l4_root_clk_div: l4_root_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&l3_iclk_div>;
clock-mult = <1>;
clock-div = <2>;
};
video1_clk2_div: video1_clk2_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&video1_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
video1_div_clk: video1_div_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&video1_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
video2_clk2_div: video2_clk2_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&video2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
video2_div_clk: video2_div_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&video2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
ipu1_gfclk_mux: ipu1_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
ti,bit-shift = <24>;
reg = <0x0520>;
assigned-clocks = <&ipu1_gfclk_mux>;
assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <28>;
reg = <0x0550>;
};
mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x0550>;
};
mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x0550>;
};
timer5_gfclk_mux: timer5_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0558>;
};
timer6_gfclk_mux: timer6_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0560>;
};
timer7_gfclk_mux: timer7_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0568>;
};
timer8_gfclk_mux: timer8_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0570>;
};
uart6_gfclk_mux: uart6_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x0580>;
};
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
&prm_clocks {
sys_clkin1: sys_clkin1 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
};
abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0118>;
};
abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x0114>;
};
abe_dpll_clk_mux: abe_dpll_clk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x010c>;
};
abe_24m_fclk: abe_24m_fclk {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
reg = <0x011c>;
ti,dividers = <8>, <16>;
};
aess_fclk: aess_fclk {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&abe_clk>;
reg = <0x0178>;
ti,max-div = <2>;
};
abe_giclk_div: abe_giclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&aess_fclk>;
reg = <0x0174>;
ti,max-div = <2>;
};
abe_lp_clk_div: abe_lp_clk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
reg = <0x01d8>;
ti,dividers = <16>, <32>;
};
abe_sys_clk_div: abe_sys_clk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
reg = <0x0120>;
ti,max-div = <2>;
};
adc_gfclk_mux: adc_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
reg = <0x01dc>;
};
sys_clk1_dclk_div: sys_clk1_dclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x01c8>;
ti,index-power-of-two;
};
sys_clk2_dclk_div: sys_clk2_dclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin2>;
ti,max-div = <64>;
reg = <0x01cc>;
ti,index-power-of-two;
};
per_abe_x1_dclk_div: per_abe_x1_dclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2_ck>;
ti,max-div = <64>;
reg = <0x01bc>;
ti,index-power-of-two;
};
dsp_gclk_div: dsp_gclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_m2_ck>;
ti,max-div = <64>;
reg = <0x018c>;
ti,index-power-of-two;
};
gpu_dclk: gpu_dclk {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gpu_m2_ck>;
ti,max-div = <64>;
reg = <0x01a0>;
ti,index-power-of-two;
};
emif_phy_dclk_div: emif_phy_dclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_m2_ck>;
ti,max-div = <64>;
reg = <0x0190>;
ti,index-power-of-two;
};
gmac_250m_dclk_div: gmac_250m_dclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_m2_ck>;
ti,max-div = <64>;
reg = <0x019c>;
ti,index-power-of-two;
};
l3init_480m_dclk_div: l3init_480m_dclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_m2_ck>;
ti,max-div = <64>;
reg = <0x01ac>;
ti,index-power-of-two;
};
usb_otg_dclk_div: usb_otg_dclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&usb_otg_clkin_ck>;
ti,max-div = <64>;
reg = <0x0184>;
ti,index-power-of-two;
};
sata_dclk_div: sata_dclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x01c0>;
ti,index-power-of-two;
};
pcie2_dclk_div: pcie2_dclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_m2_ck>;
ti,max-div = <64>;
reg = <0x01b8>;
ti,index-power-of-two;
};
pcie_dclk_div: pcie_dclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&apll_pcie_m2_ck>;
ti,max-div = <64>;
reg = <0x01b4>;
ti,index-power-of-two;
};
emu_dclk_div: emu_dclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x0194>;
ti,index-power-of-two;
};
secure_32k_dclk_div: secure_32k_dclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&secure_32k_clk_src_ck>;
ti,max-div = <64>;
reg = <0x01c4>;
ti,index-power-of-two;
};
clkoutmux0_clk_mux: clkoutmux0_clk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x0158>;
};
clkoutmux1_clk_mux: clkoutmux1_clk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x015c>;
};
clkoutmux2_clk_mux: clkoutmux2_clk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x0160>;
};
custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin1>;
clock-mult = <1>;
clock-div = <2>;
};
eve_clk: eve_clk {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
reg = <0x0180>;
};
hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0164>;
};
mlb_clk: mlb_clk {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mlb_clkin_ck>;
ti,max-div = <64>;
reg = <0x0134>;
ti,index-power-of-two;
};
mlbp_clk: mlbp_clk {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mlbp_clkin_ck>;
ti,max-div = <64>;
reg = <0x0130>;
ti,index-power-of-two;
};
per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2_ck>;
ti,max-div = <64>;
reg = <0x0138>;
ti,index-power-of-two;
};
timer_sys_clk_div: timer_sys_clk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
reg = <0x0144>;
ti,max-div = <2>;
};
video1_dpll_clk_mux: video1_dpll_clk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0168>;
};
video2_dpll_clk_mux: video2_dpll_clk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x016c>;
};
wkupaon_iclk_mux: wkupaon_iclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
gpio1_dbclk: gpio1_dbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1838>;
};
dcan1_sys_clk_mux: dcan1_sys_clk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
ti,bit-shift = <24>;
reg = <0x1888>;
};
timer1_gfclk_mux: timer1_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1840>;
};
uart10_gfclk_mux: uart10_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1880>;
};
};
&cm_core_clocks {
dpll_pcie_ref_ck: dpll_pcie_ref_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&sys_clkin1>;
reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
};
dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0210>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
compatible = "ti,mux-clock";
clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
#clock-cells = <0>;
reg = <0x021c 0x4>;
ti,bit-shift = <7>;
};
apll_pcie_ck: apll_pcie_ck {
#clock-cells = <0>;
compatible = "ti,dra7-apll-clock";
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
reg = <0x021c>, <0x0220>;
};
optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <8>;
};
optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <8>;
};
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x021c>;
ti,dividers = <2>, <1>;
ti,bit-shift = <8>;
ti,max-div = <2>;
};
optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <9>;
};
optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <9>;
};
optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <10>;
};
optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <10>;
};
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
apll_pcie_m2_ck: apll_pcie_m2_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_per_byp_mux: dpll_per_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x014c>;
};
dpll_per_ck: dpll_per_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
dpll_per_m2_ck: dpll_per_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0150>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
func_96m_aon_dclk_div: func_96m_aon_dclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dpll_usb_byp_mux: dpll_usb_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x018c>;
};
dpll_usb_ck: dpll_usb_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
dpll_usb_m2_ck: dpll_usb_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
reg = <0x0190>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
reg = <0x0210>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_x2_ck: dpll_per_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_per_ck>;
};
dpll_per_h11x2_ck: dpll_per_h11x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0158>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_h12x2_ck: dpll_per_h12x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x015c>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_h13x2_ck: dpll_per_h13x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0160>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_h14x2_ck: dpll_per_h14x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0164>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_m2x2_ck: dpll_per_m2x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0150>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_usb_ck>;
clock-mult = <1>;
clock-div = <1>;
};
func_128m_clk: func_128m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_per_h11x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
func_12m_fclk: func_12m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
};
func_24m_clk: func_24m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
func_48m_fclk: func_48m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
func_96m_fclk: func_96m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
l3init_60m_fclk: l3init_60m_fclk {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_m2_ck>;
reg = <0x0104>;
ti,dividers = <1>, <8>;
};
clkout2_clk: clkout2_clk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkoutmux2_clk_mux>;
ti,bit-shift = <8>;
reg = <0x06b0>;
};
l3init_960m_gfclk: l3init_960m_gfclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x06c0>;
};
dss_32khz_clk: dss_32khz_clk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <11>;
reg = <0x1120>;
};
dss_48mhz_clk: dss_48mhz_clk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_48m_fclk>;
ti,bit-shift = <9>;
reg = <0x1120>;
};
dss_dss_clk: dss_dss_clk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_h12x2_ck>;
ti,bit-shift = <8>;
reg = <0x1120>;
ti,set-rate-parent;
};
dss_hdmi_clk: dss_hdmi_clk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&hdmi_dpll_clk_mux>;
ti,bit-shift = <10>;
reg = <0x1120>;
};
dss_video1_clk: dss_video1_clk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video1_dpll_clk_mux>;
ti,bit-shift = <12>;
reg = <0x1120>;
};
dss_video2_clk: dss_video2_clk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video2_dpll_clk_mux>;
ti,bit-shift = <13>;
reg = <0x1120>;
};
gpio2_dbclk: gpio2_dbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1760>;
};
gpio3_dbclk: gpio3_dbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1768>;
};
gpio4_dbclk: gpio4_dbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1770>;
};
gpio5_dbclk: gpio5_dbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1778>;
};
gpio6_dbclk: gpio6_dbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1780>;
};
gpio7_dbclk: gpio7_dbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1810>;
};
gpio8_dbclk: gpio8_dbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1818>;
};
mmc1_clk32k: mmc1_clk32k {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1328>;
};
mmc2_clk32k: mmc2_clk32k {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1330>;
};
mmc3_clk32k: mmc3_clk32k {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1820>;
};
mmc4_clk32k: mmc4_clk32k {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1828>;
};
sata_ref_clk: sata_ref_clk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin1>;
ti,bit-shift = <8>;
reg = <0x1388>;
};
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
ti,bit-shift = <8>;
reg = <0x13f0>;
};
usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
ti,bit-shift = <8>;
reg = <0x1340>;
};
usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0640>;
};
usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0688>;
};
usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0698>;
};
atl_dpll_clk_mux: atl_dpll_clk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
ti,bit-shift = <24>;
reg = <0x0c00>;
};
atl_gfclk_mux: atl_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
ti,bit-shift = <26>;
reg = <0x0c00>;
};
rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
ti,bit-shift = <24>;
reg = <0x13d0>;
};
gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_gmac_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
gmac_rft_clk_mux: gmac_rft_clk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
ti,bit-shift = <25>;
reg = <0x13d0>;
};
gpu_core_gclk_mux: gpu_core_gclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <24>;
reg = <0x1220>;
assigned-clocks = <&gpu_core_gclk_mux>;
assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <26>;
reg = <0x1220>;
assigned-clocks = <&gpu_hyd_gclk_mux>;
assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
l3instr_ts_gclk_div: l3instr_ts_gclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&wkupaon_iclk_mux>;
ti,bit-shift = <24>;
reg = <0x0e50>;
ti,dividers = <8>, <16>, <32>;
};
mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <28>;
reg = <0x1860>;
};
mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1860>;
};
mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1860>;
};
mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1868>;
};
mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1868>;
};
mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1898>;
};
mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1898>;
};
mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1878>;
};
mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1878>;
};
mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1904>;
};
mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1904>;
};
mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1908>;
};
mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1908>;
};
mcasp8_ahclkx_mux: mcasp8_ahclkx_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <22>;
reg = <0x1890>;
};
mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <24>;
reg = <0x1890>;
};
mmc1_fclk_mux: mmc1_fclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1328>;
};
mmc1_fclk_div: mmc1_fclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc1_fclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1328>;
ti,index-power-of-two;
};
mmc2_fclk_mux: mmc2_fclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1330>;
};
mmc2_fclk_div: mmc2_fclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc2_fclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1330>;
ti,index-power-of-two;
};
mmc3_gfclk_mux: mmc3_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1820>;
};
mmc3_gfclk_div: mmc3_gfclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc3_gfclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1820>;
ti,index-power-of-two;
};
mmc4_gfclk_mux: mmc4_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1828>;
};
mmc4_gfclk_div: mmc4_gfclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc4_gfclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1828>;
ti,index-power-of-two;
};
qspi_gfclk_mux: qspi_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
ti,bit-shift = <24>;
reg = <0x1838>;
};
qspi_gfclk_div: qspi_gfclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&qspi_gfclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1838>;
ti,index-power-of-two;
};
timer10_gfclk_mux: timer10_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1728>;
};
timer11_gfclk_mux: timer11_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1730>;
};
timer13_gfclk_mux: timer13_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x17c8>;
};
timer14_gfclk_mux: timer14_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x17d0>;
};
timer15_gfclk_mux: timer15_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x17d8>;
};
timer16_gfclk_mux: timer16_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1830>;
};
timer2_gfclk_mux: timer2_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1738>;
};
timer3_gfclk_mux: timer3_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1740>;
};
timer4_gfclk_mux: timer4_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1748>;
};
timer9_gfclk_mux: timer9_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1750>;
};
uart1_gfclk_mux: uart1_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1840>;
};
uart2_gfclk_mux: uart2_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1848>;
};
uart3_gfclk_mux: uart3_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1850>;
};
uart4_gfclk_mux: uart4_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1858>;
};
uart5_gfclk_mux: uart5_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1870>;
};
uart7_gfclk_mux: uart7_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x18d0>;
};
uart8_gfclk_mux: uart8_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x18e0>;
};
uart9_gfclk_mux: uart9_gfclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x18e8>;
};
vip1_gclk_mux: vip1_gclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1020>;
};
vip2_gclk_mux: vip2_gclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1028>;
};
vip3_gclk_mux: vip3_gclk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1030>;
};
};
&cm_core_clockdomains {
coreaon_clkdm: coreaon_clkdm {
compatible = "ti,clockdomain";
clocks = <&dpll_usb_ck>;
};
};
&scm_conf_clocks {
dss_deshdcp_clk: dss_deshdcp_clk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3_iclk_div>;
ti,bit-shift = <0>;
reg = <0x558>;
};
sys_32k_ck: sys_32k_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
ti,bit-shift = <8>;
reg = <0x6c4>;
};
ehrpwm0_tbclk: ehrpwm0_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <20>;
reg = <0x0558>;
};
ehrpwm1_tbclk: ehrpwm1_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <21>;
reg = <0x0558>;
};
ehrpwm2_tbclk: ehrpwm2_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <22>;
reg = <0x0558>;
};
};
/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/clk/ti-dra7-atl.h>
/ {
#if 0
jamr3_sound {
compatible = "simple-audio-card";
simple-audio-card,name = "DRA7xx-JAMR3";
simple-audio-card,widgets =
"Line", "Line Out",
"Line", "Line In";
simple-audio-card,routing =
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&jamr3_sound_master>;
simple-audio-card,frame-master = <&jamr3_sound_master>;
simple-audio-card,bitclock-inversion;
jamr3_sound_master: simple-audio-card,cpu {
sound-dai = <&mcasp6>;
system-clock-frequency = <11289600>;
};
simple-audio-card,codec {
sound-dai = <&tlv320aic3106a>;
clocks = <&atl_clkin1_ck>;
};
};
#endif
gatemp {
compatible = "hwspinlock-user";
hwlocks = <&hwspinlock 0>,
<&hwspinlock 1>,
<&hwspinlock 2>,
<&hwspinlock 3>,
<&hwspinlock 4>,
<&hwspinlock 5>,
<&hwspinlock 6>,
<&hwspinlock 7>,
<&hwspinlock 8>,
<&hwspinlock 9>;
};
sr0 {
compatible = "generic-uio";
reg = <0x0 0xbfb00000 0x0 0x100000>;
};
};
&reserved_mem {
/* Required by cmem driver used by radio */
cmem_radio: cmem@95400000 {
reg = <0x0 0x95400000 0x0 0x400000>;
no-map;
status = "okay";
};
dsp1_sr0: dsp1_sr0@bfb00000 {
reg = <0x0 0xbfb00000 0x0 0x100000>;
no-map;
status = "okay";
};
};
&gpio6 {
p20 {
/* Radio reset GPIO */
gpio-hog;
gpios = <1 GPIO_ACTIVE_LOW>;
output-low;
line-name = "radio_rst";
};
};
&atl {
atl1 {
bws = <DRA7_ATL_WS_MCASP2_FSX>;
aws = <DRA7_ATL_WS_MCASP6_FSX>;
};
};
&mcasp2 {
assigned-clocks = <&mcasp2_ahclkx_mux>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "disabled";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 8 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
2 0 0 0 0 0 0 0
>;
shared-dai;
};
&mcasp6 {
#sound-dai-cells = <0>;
assigned-clocks = <&mcasp6_ahclkx_mux>;
assigned-clock-parents = <&atl_clkin1_ck>;
status = "disabled";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializer */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
shared-dai;
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
pcf_jamr3_21: pcf8575@21 {
compatible = "nxp,pcf8575";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c_p3_exp {
#if 0
tlv320aic3106a: tlv320aic3106@18 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
status = "disabled";
reg = <0x18>;
adc-settle-ms = <40>;
ai3x-micbias-vg = <1>; /* 2.0V */
name-prefix = "J3A";
status = "okay";
/* Regulators */
AVDD-supply = <&evm_3v3_sw>;
IOVDD-supply = <&evm_3v3_sw>;
DRVDD-supply = <&evm_3v3_sw>;
DVDD-supply = <&aic_dvdd>;
};
tlv320aic3106b: tlv320aic3106@19 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
status = "disabled";
reg = <0x19>;
adc-settle-ms = <40>;
ai3x-micbias-vg = <1>; /* 2.0V */
name-prefix = "J3B";
status = "okay";
/* Regulators */
AVDD-supply = <&evm_3v3_sw>;
IOVDD-supply = <&evm_3v3_sw>;
DRVDD-supply = <&evm_3v3_sw>;
DVDD-supply = <&aic_dvdd>;
};
tlv320aic3106c: tlv320aic3106@1a {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
status = "disabled";
reg = <0x1a>;
adc-settle-ms = <40>;
ai3x-micbias-vg = <1>; /* 2.0V */
name-prefix = "J3C";
status = "okay";
/* Regulators */
AVDD-supply = <&evm_3v3_sw>;
IOVDD-supply = <&evm_3v3_sw>;
DRVDD-supply = <&evm_3v3_sw>;
DVDD-supply = <&aic_dvdd>;
};
#endif
#if 1
tvp_5158: tvp5158@58 {
compatible= "ti,tvp5158";
reg = <0x58>;
port {
tvp_decoder: endpoint@0 {
//channels = <0 2 4 6>;
channels = <0>;
//pixel-mux;
};
};
};
#else
tvp_5158: tvp5158@58 {
compatible= "ti,tvp5158";
reg = <0x58>;
port {
tvp_decoder: endpoint@0 {
channels = <0 2 4 6>;
};
};
};
#endif
};
&video_in {
endpoint {
slave-mode;
remote-endpoint = <&tvp_decoder>;
};
};
/*
* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "dra72-evm-common.dtsi"
#include "dt-bindings/pinmux/mux_dra7xx.h"
/ {
model = "TI DRA722 Louis 20170516 13:50";
aliases {
display0 = &hdmi0;
display1 = &lcd2;
sound1 = &hdmi;
};
lcd2: display@2 {
compatible = "omapdss,panel-dpi", "panel-dpi";
status = "ok";
label = "lcd";
//enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
// 1920x1200@60
// 1920x1200@30
// 1920x1080@60
// 1920x1080@30
// 1280x720@30
// 800x480@30
/*
// 1920x1200@60
// (1920+226)*(1200+32)*60=158632320
panel-timing {
clock-frequency = <158000000>;
hactive = <1920>;
vactive = <1200>;
hfront-porch = <210>;
hback-porch = <16>;
hsync-len = <30>;
vback-porch = <10>;
vfront-porch = <22>;
vsync-len = <13>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
*/
/*
// 1920x1200@30
// (1920+226)*(1200+32)*30=79316160
panel-timing {
clock-frequency = <79000000>;
hactive = <1920>;
vactive = <1200>;
hfront-porch = <210>;
hback-porch = <16>;
hsync-len = <30>;
vback-porch = <10>;
vfront-porch = <22>;
vsync-len = <13>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
*/
/*
// 1920x1080@60
// (1920+226)*(1080+32)*60=142181120
panel-timing {
clock-frequency = <142000000>;
hactive = <1920>;
vactive = <1080>;
hfront-porch = <210>;
hback-porch = <16>;
hsync-len = <30>;
vback-porch = <10>;
vfront-porch = <22>;
vsync-len = <13>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
*/
// 1920x1080@30
// (1920+226)*(1080+32)*30=71590560
panel-timing {
clock-frequency = <72000000>;
hactive = <1920>;
vactive = <1080>;
hfront-porch = <210>;
hback-porch = <16>;
hsync-len = <30>;
vback-porch = <10>;
vfront-porch = <22>;
vsync-len = <13>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
/*
// 1280x720@30
// (1280+226)*(720+32)*30=33975360
panel-timing {
clock-frequency = <24000000>;
hactive = <1280>;
vactive = <720>;
hfront-porch = <210>;
hback-porch = <16>;
hsync-len = <30>;
vback-porch = <10>;
vfront-porch = <22>;
vsync-len = <13>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
*/
/*
// 800x480@30
// (800+226)*(480+32)*30=15759360
panel-timing {
clock-frequency = <16000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <210>;
hback-porch = <16>;
hsync-len = <30>;
vback-porch = <10>;
vfront-porch = <22>;
vsync-len = <13>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
*/
port {
lcd2_in: endpoint {
remote-endpoint = <&dpi2_out>;
};
};
};
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
};
reserved_mem: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ipu2_cma_pool: ipu2_cma@95800000 {
compatible = "shared-dma-pool";
reg = <0x0 0x95800000 0x0 0x3800000>;
reusable;
status = "okay";
};
dsp1_cma_pool: dsp1_cma@99000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x99000000 0x0 0x4000000>;
reusable;
status = "okay";
};
ipu1_cma_pool: ipu1_cma@9d000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x9d000000 0x0 0x2000000>;
reusable;
status = "okay";
};
};
};
&tps65917_regulators {
ldo2_reg: ldo2 {
/* LDO2_OUT --> TP1017 (UNUSED) */
regulator-name = "ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-allow-bypass;
};
};
&dra7_pmx_core {
vin2a_pins: pinmux_vin2a_pins {
pinctrl-single,pins = <
0x23c (PIN_INPUT | MUX_MODE4) // 0x23C gpio5_15 V1 mdio_mclk.vin2a_clk0
0x240 (PIN_INPUT | MUX_MODE4) // 0x240 gpio5_16 U4 mdio_d.vin2a_d0
0x248 (PIN_INPUT | MUX_MODE4) // 0x248 gpio5_18 V2 uart3_rxd.vin2a_d1
0x24c (PIN_INPUT | MUX_MODE4) // 0x24C gpio5_19 Y1 uart3_txd.vin2a_d2
0x250 (PIN_INPUT | MUX_MODE4) // 0x250 gpio5_20 W9 rgmii0_txc.vin2a_d3
0x254 (PIN_INPUT | MUX_MODE4) // 0x254 gpio5_21 V9 rgmii0_txctl.vin2a_d4
0x268 (PIN_INPUT | MUX_MODE4) // 0x268 U5 gpio5_26 rgmii_rxc.vin2a_d5
0x26c (PIN_INPUT | MUX_MODE4) // 0x26C gpio5_27 V5 rgmii0_rxctl.vin2a_d6
0x270 (PIN_INPUT | MUX_MODE4) // 0x270 gpio5_28 V4 rgmii0_rxd3.vin2a_d7
>;
};
vout3_pins: pinmux_vout3_pins {
pinctrl-single,pins = <
GPMC_A0 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A0.vout3_d16 GPIO7_3 R6 */
GPMC_A1 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A1.vout3_d17 */
GPMC_A2 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A2.vout3_d18 */
GPMC_A3 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A3.vout3_d18 */
GPMC_A4 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A4.vout3_d20 */
GPMC_A5 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A5.vout3_d21 */
GPMC_A6 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A6.vout3_d22 */
GPMC_A7 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A7.vout3_d23 */
GPMC_AD8 (PIN_OUTPUT | MUX_MODE3) /* GPMC_AD8.vout3_d8 */
GPMC_AD9 (PIN_OUTPUT | MUX_MODE3) /* GPMC_AD9.vout3_d9 */
GPMC_AD10 (PIN_OUTPUT | MUX_MODE3) /* GPMC_AD10.vout3_d10 */
GPMC_AD11 (PIN_OUTPUT | MUX_MODE3) /* GPMC_AD11.vout3_d11 */
GPMC_AD12 (PIN_OUTPUT | MUX_MODE3) /* GPMC_AD12.vout3_d12 */
GPMC_AD13 (PIN_OUTPUT | MUX_MODE3) /* GPMC_AD13.vout3_d13 */
GPMC_AD14 (PIN_OUTPUT | MUX_MODE3) /* GPMC_AD14.vout3_d14 */
GPMC_AD15 (PIN_OUTPUT | MUX_MODE3) /* GPMC_AD15.vout3_d15 */
GPMC_AD0 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A0.vout3_d0 */
GPMC_AD1 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A0.vout3_d1 */
GPMC_AD2 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A0.vout3_d2 */
GPMC_AD3 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A0.vout3_d3 */
GPMC_AD4 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A0.vout3_d4 */
GPMC_AD5 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A0.vout3_d5 */
GPMC_AD6 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A0.vout3_d6 */
GPMC_AD7 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A0.vout3_d7 */
GPMC_A11 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A11.vout3_fld */
GPMC_A10 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A10.vout3_de */
GPMC_A8 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A8.vout3_hsync */
GPMC_A9 (PIN_OUTPUT | MUX_MODE3) /* GPMC_A9.vout3_vsync */
GPMC_CS3 (PIN_OUTPUT | MUX_MODE3) /* GPMC_CS3.vout3_clk */
VIN2A_D9 (PIN_OUTPUT | MUX_MODE14) /* VIN2A_D9.gpio4_10 DISP_RESETQ */
>;
};
uart1_pins: uart1_pins {
pinctrl-single,pins = <
// i2c_3
GPMC_ADVN_ALE (PIN_INPUT | MUX_MODE8) /* gpmc_advn_ale.i2c3_sda -> 8 */
GPMC_CLK (PIN_INPUT | MUX_MODE8) /* gpmc_clk.i2c3_scl -> 8 */
// i2c_4
MMC1_SDCD (PIN_INPUT | MUX_MODE4) /* mmc1_sdcd.i2c4_sda -> 4 */
MMC1_SDWP (PIN_INPUT | MUX_MODE4) /* mmc1_sdwp.i2c4_scl -> 4 */
// i2c_5
MCASP1_AXR0 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda -> 10 */
MCASP1_AXR1 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl -> 10 */
// spi 1.0, 1.1, 1.3
SPI1_SCLK (PIN_INPUT | MUX_MODE0) /* 0x3A4 */
SPI1_D1 (PIN_INPUT | MUX_MODE0) /* 0x3A8 */
SPI1_D0 (PIN_INPUT | MUX_MODE0) /* 0x3AC */
SPI1_CS0 (PIN_INPUT | MUX_MODE0) /* 0x3B0 */
SPI1_CS1 (PIN_INPUT | MUX_MODE0) /* 0x3B4 */
SPI1_CS3 (PIN_INPUT | MUX_MODE0) /* 0x3BC */
// spi 2.0
SPI2_SCLK ( PIN_INPUT | MUX_MODE0 ) /* 0x3C0 */
SPI2_D1 ( PIN_INPUT | MUX_MODE0 ) /* 0x3C4 */
SPI2_D0 ( PIN_INPUT | MUX_MODE0 ) /* 0x3C8 */
SPI2_CS0 ( PIN_INPUT | MUX_MODE0 ) /* 0x3CC */
// spi 3.0
VOUT1_CLK (PIN_INPUT | MUX_MODE8) // DAB_SPI_CS GPIO4_19
VOUT1_DE (PIN_INPUT | MUX_MODE8) // DAB_SPI_MISO GPIO4_20
VOUT1_HSYNC (PIN_INPUT | MUX_MODE8) // DAB_SPI_MOSI GPIO4_22
VOUT1_VSYNC (PIN_INPUT | MUX_MODE8) // DAB_SPI_SCK GPIO4_23
// BT656 vin4b
MDIO_MCLK (PIN_INPUT | MUX_MODE5) /* 0x23C */ // BT656_CLK1
MDIO_D (PIN_INPUT | MUX_MODE5) /* 0x240 */ // BT656_DO
UART3_RXD (PIN_INPUT | MUX_MODE5) /* 0x248 */ // BT656_D1
UART3_TXD (PIN_INPUT | MUX_MODE5) /* 0x24C */ // BT656_D2
RGMII0_TXC (PIN_INPUT | MUX_MODE5) /* 0x250 */ // BT656_D3
RGMII0_TXCTL (PIN_INPUT | MUX_MODE5) /* 0x254 */ // BT656_D4
RGMII0_RXC (PIN_INPUT | MUX_MODE5) /* 0x268 */ // BT656_D5
RGMII0_RXCTL (PIN_INPUT | MUX_MODE5) /* 0x26C */ // BT656_D6
RGMII0_RXD3 (PIN_INPUT | MUX_MODE5) /* 0x270 */ // BT656_D7
RGMII0_RXD2 (PIN_INPUT | MUX_MODE14) /* 0x274 */
VIN2A_DE0 (PIN_INPUT | MUX_MODE14) /* 0x158 */
//===================================================================================
//GPMC_AD0 (PIN_INPUT | MUX_MODE14) /* 0x000 */
//GPMC_AD1 (PIN_INPUT | MUX_MODE14) /* 0x004 */
//GPMC_AD2 (PIN_INPUT | MUX_MODE14) /* 0x008 */
//GPMC_AD3 (PIN_INPUT | MUX_MODE14) /* 0x00C */
//GPMC_AD4 (PIN_INPUT | MUX_MODE14) /* 0x010 */
//GPMC_AD5 (PIN_INPUT | MUX_MODE14) /* 0x014 */
//GPMC_AD6 (PIN_INPUT | MUX_MODE14) /* 0x018 */
//GPMC_AD7 (PIN_INPUT | MUX_MODE14) /* 0x01C */
//GPMC_AD8 (PIN_INPUT | MUX_MODE14) /* 0x020 */
//GPMC_AD9 (PIN_INPUT | MUX_MODE14) /* 0x024 */
//GPMC_AD10 (PIN_INPUT | MUX_MODE14) /* 0x028 */
//GPMC_AD11 (PIN_INPUT | MUX_MODE14) /* 0x02C */
//GPMC_AD12 (PIN_INPUT | MUX_MODE14) /* 0x030 */
//GPMC_AD13 (PIN_INPUT | MUX_MODE14) /* 0x034 */
//GPMC_AD14 (PIN_INPUT | MUX_MODE14) /* 0x038 */
//GPMC_AD15 (PIN_INPUT | MUX_MODE14) /* 0x03C */
//GPMC_A0 (PIN_INPUT | MUX_MODE14) /* 0x040 */
//GPMC_A1 (PIN_INPUT | MUX_MODE14) /* 0x044 */
//GPMC_A2 (PIN_INPUT | MUX_MODE14) /* 0x048 */
//GPMC_A3 (PIN_INPUT | MUX_MODE14) /* 0x04C */
//GPMC_A4 (PIN_INPUT | MUX_MODE14) /* 0x050 */
//GPMC_A5 (PIN_INPUT | MUX_MODE14) /* 0x054 */
//GPMC_A6 (PIN_INPUT | MUX_MODE14) /* 0x058 */
//GPMC_A7 (PIN_INPUT | MUX_MODE14) /* 0x05C */
//GPMC_A8 (PIN_INPUT | MUX_MODE14) /* 0x060 */
//GPMC_A9 (PIN_INPUT | MUX_MODE14) /* 0x064 */
//GPMC_A10 (PIN_INPUT | MUX_MODE14) /* 0x068 */
//GPMC_A11 (PIN_INPUT | MUX_MODE14) /* 0x06C */
GPMC_A12 (PIN_INPUT | MUX_MODE14) /* 0x070 */
GPMC_A13 (PIN_INPUT | MUX_MODE14) /* 0x074 */
GPMC_A14 (PIN_INPUT | MUX_MODE14) /* 0x078 */
GPMC_A15 (PIN_INPUT | MUX_MODE14) /* 0x07C */
GPMC_A16 (PIN_INPUT | MUX_MODE14) /* 0x080 */
GPMC_A17 (PIN_INPUT | MUX_MODE14) /* 0x084 */
GPMC_A18 (PIN_INPUT | MUX_MODE14) /* 0x088 */
//GPMC_A19 (PIN_INPUT | MUX_MODE14) /* 0x08C */
//GPMC_A20 (PIN_INPUT | MUX_MODE14) /* 0x090 */
//GPMC_A21 (PIN_INPUT | MUX_MODE14) /* 0x094 */
//GPMC_A22 (PIN_INPUT | MUX_MODE14) /* 0x098 */
//GPMC_A23 (PIN_INPUT | MUX_MODE14) /* 0x09C */
//GPMC_A24 (PIN_INPUT | MUX_MODE14) /* 0x0A0 */
//GPMC_A25 (PIN_INPUT | MUX_MODE14) /* 0x0A4 */
//GPMC_A26 (PIN_INPUT | MUX_MODE14) /* 0x0A8 */
//GPMC_A27 (PIN_INPUT | MUX_MODE14) /* 0x0AC */
//GPMC_CS1 (PIN_INPUT | MUX_MODE14) /* 0x0B0 */
GPMC_CS0 (PIN_INPUT | MUX_MODE14) /* 0x0B4 */
GPMC_CS2 (PIN_INPUT | MUX_MODE14) /* 0x0B8 */
//GPMC_CS3 (PIN_INPUT | MUX_MODE14) /* 0x0BC */
//GPMC_CLK (PIN_INPUT | MUX_MODE14) /* 0x0C0 */
//GPMC_ADVN_ALE (PIN_INPUT | MUX_MODE14) /* 0x0C4 */
GPMC_OEN_REN (PIN_INPUT | MUX_MODE14) /* 0x0C8 */
GPMC_WEN (PIN_INPUT | MUX_MODE14) /* 0x0CC */
GPMC_BEN0 (PIN_INPUT | MUX_MODE14) /* 0x0D0 */
GPMC_BEN1 (PIN_INPUT | MUX_MODE14) /* 0x0D4 */
GPMC_WAIT0 (PIN_INPUT | MUX_MODE14) /* 0x0D8 */
VIN1A_CLK0 (PIN_INPUT | MUX_MODE14) /* 0x0DC */
VIN1B_CLK1 (PIN_INPUT | MUX_MODE14) /* 0x0E0 */
VIN1A_DE0 (PIN_INPUT | MUX_MODE14) /* 0x0E4 */
VIN1A_FLD0 (PIN_INPUT | MUX_MODE14) /* 0x0E8 */
VIN1A_HSYNC0 (PIN_INPUT | MUX_MODE14) /* 0x0EC */
VIN1A_VSYNC0 (PIN_INPUT | MUX_MODE14) /* 0x0F0 */
VIN1A_D0 (PIN_INPUT | MUX_MODE14) /* 0x0F4 */
VIN1A_D1 (PIN_INPUT | MUX_MODE14) /* 0x0F8 */
VIN1A_D2 (PIN_INPUT | MUX_MODE14) /* 0x0FC */
VIN1A_D3 (PIN_INPUT | MUX_MODE14) /* 0x100 */
VIN1A_D4 (PIN_INPUT | MUX_MODE14) /* 0x104 */
VIN1A_D5 (PIN_INPUT | MUX_MODE14) /* 0x108 */
VIN1A_D6 (PIN_INPUT | MUX_MODE14) /* 0x10C */
VIN1A_D7 (PIN_INPUT | MUX_MODE14) /* 0x110 */
VIN1A_D8 (PIN_INPUT | MUX_MODE14) /* 0x114 */
VIN1A_D9 (PIN_INPUT | MUX_MODE14) /* 0x118 */
VIN1A_D10 (PIN_INPUT | MUX_MODE14) /* 0x11C */
VIN1A_D11 (PIN_INPUT | MUX_MODE14) /* 0x120 */
VIN1A_D12 (PIN_INPUT | MUX_MODE14) /* 0x124 */
VIN1A_D13 (PIN_INPUT | MUX_MODE14) /* 0x128 */
VIN1A_D14 (PIN_INPUT | MUX_MODE14) /* 0x12C */
VIN1A_D15 (PIN_INPUT | MUX_MODE14) /* 0x130 */
VIN1A_D16 (PIN_INPUT | MUX_MODE14) /* 0x134 */
VIN1A_D17 (PIN_INPUT | MUX_MODE14) /* 0x138 */
VIN1A_D18 (PIN_INPUT | MUX_MODE14) /* 0x13C */
VIN1A_D19 (PIN_INPUT | MUX_MODE14) /* 0x140 */
VIN1A_D20 (PIN_INPUT | MUX_MODE14) /* 0x144 */
VIN1A_D21 (PIN_INPUT | MUX_MODE14) /* 0x148 */
VIN1A_D22 (PIN_INPUT | MUX_MODE14) /* 0x14C */
VIN1A_D23 (PIN_INPUT | MUX_MODE14) /* 0x150 */
VIN2A_CLK0 (PIN_INPUT | MUX_MODE14) /* 0x154 */
// VIN2A_DE0 (PIN_INPUT | MUX_MODE14) /* 0x158 */
VIN2A_FLD0 (PIN_INPUT | MUX_MODE14) /* 0x15C */
VIN2A_HSYNC0 (PIN_INPUT | MUX_MODE14) /* 0x160 */
VIN2A_VSYNC0 (PIN_INPUT | MUX_MODE14) /* 0x164 */
VIN2A_D0 (PIN_INPUT | MUX_MODE14) /* 0x168 */
VIN2A_D1 (PIN_INPUT | MUX_MODE14) /* 0x16C */
//VIN2A_D2 (PIN_INPUT | MUX_MODE14) /* 0x170 */
//VIN2A_D3 (PIN_INPUT | MUX_MODE14) /* 0x174 */
//VIN2A_D4 (PIN_INPUT | MUX_MODE14) /* 0x178 */
//VIN2A_D5 (PIN_INPUT | MUX_MODE14) /* 0x17C */
VIN2A_D6 (PIN_INPUT | MUX_MODE14) /* 0x180 */
VIN2A_D7 (PIN_INPUT | MUX_MODE14) /* 0x184 */
//VIN2A_D8 (PIN_INPUT | MUX_MODE14) /* 0x188 */
//VIN2A_D9 (PIN_INPUT | MUX_MODE14) /* 0x18C */
VIN2A_D10 (PIN_INPUT | MUX_MODE14) /* 0x190 */
VIN2A_D11 (PIN_INPUT | MUX_MODE14) /* 0x194 */
VIN2A_D12 (PIN_INPUT | MUX_MODE14) /* 0x198 */
VIN2A_D13 (PIN_INPUT | MUX_MODE14) /* 0x19C */
VIN2A_D14 (PIN_INPUT | MUX_MODE14) /* 0x1A0 */
VIN2A_D15 (PIN_INPUT | MUX_MODE14) /* 0x1A4 */
VIN2A_D16 (PIN_INPUT | MUX_MODE14) /* 0x1A8 */
VIN2A_D17 (PIN_INPUT | MUX_MODE14) /* 0x1AC */
VIN2A_D18 (PIN_INPUT | MUX_MODE14) /* 0x1B0 */
VIN2A_D19 (PIN_INPUT | MUX_MODE14) /* 0x1B4 */
VIN2A_D20 (PIN_INPUT | MUX_MODE14) /* 0x1B8 */
VIN2A_D21 (PIN_INPUT | MUX_MODE14) /* 0x1BC */
VIN2A_D22 (PIN_INPUT | MUX_MODE14) /* 0x1C0 */
VIN2A_D23 (PIN_INPUT | MUX_MODE14) /* 0x1C4 */
//VOUT1_CLK (PIN_INPUT | MUX_MODE14) /* 0x1C8 */
//VOUT1_DE (PIN_INPUT | MUX_MODE14) /* 0x1CC */
VOUT1_FLD (PIN_INPUT | MUX_MODE14) /* 0x1D0 */
//VOUT1_HSYNC (PIN_INPUT | MUX_MODE14) /* 0x1D4 */
//VOUT1_VSYNC (PIN_INPUT | MUX_MODE14) /* 0x1D8 */
//VOUT1_D0 (PIN_INPUT | MUX_MODE14) /* 0x1DC */ // uart5
//VOUT1_D1 (PIN_INPUT | MUX_MODE14) /* 0x1E0 */ // uart5
VOUT1_D2 (PIN_INPUT | MUX_MODE14) /* 0x1E4 */
VOUT1_D3 (PIN_INPUT | MUX_MODE14) /* 0x1E8 */
VOUT1_D4 (PIN_INPUT | MUX_MODE14) /* 0x1EC */
VOUT1_D5 (PIN_INPUT | MUX_MODE14) /* 0x1F0 */
VOUT1_D6 (PIN_INPUT | MUX_MODE14) /* 0x1F4 */
VOUT1_D7 (PIN_INPUT | MUX_MODE14) /* 0x1F8 */
//VOUT1_D8 (PIN_INPUT | MUX_MODE14) /* 0x1FC */ // uart6
//VOUT1_D9 (PIN_INPUT | MUX_MODE14) /* 0x200 */ // uart6
VOUT1_D10 (PIN_INPUT | MUX_MODE14) /* 0x204 */
VOUT1_D11 (PIN_INPUT | MUX_MODE14) /* 0x208 */
VOUT1_D12 (PIN_INPUT | MUX_MODE14) /* 0x20C */
VOUT1_D13 (PIN_INPUT | MUX_MODE14) /* 0x210 */
VOUT1_D14 (PIN_INPUT | MUX_MODE14) /* 0x214 */
VOUT1_D15 (PIN_INPUT | MUX_MODE14) /* 0x218 */
VOUT1_D16 (PIN_INPUT | MUX_MODE14) /* 0x21C */
VOUT1_D17 (PIN_INPUT | MUX_MODE14) /* 0x220 */
VOUT1_D18 (PIN_INPUT | MUX_MODE14) /* 0x224 */
VOUT1_D19 (PIN_INPUT | MUX_MODE14) /* 0x228 */
VOUT1_D20 (PIN_INPUT | MUX_MODE14) /* 0x22C */
VOUT1_D21 (PIN_INPUT | MUX_MODE14) /* 0x230 */
VOUT1_D22 (PIN_INPUT | MUX_MODE14) /* 0x234 */
VOUT1_D23 (PIN_INPUT | MUX_MODE14) /* 0x238 */
// MDIO_MCLK (PIN_INPUT | MUX_MODE14) /* 0x23C */
// MDIO_D (PIN_INPUT | MUX_MODE14) /* 0x240 */
RMII_MHZ_50_CLK (PIN_INPUT | MUX_MODE14) /* 0x244 */
// UART3_RXD (PIN_INPUT | MUX_MODE14) /* 0x248 */
// UART3_TXD (PIN_INPUT | MUX_MODE14) /* 0x24C */
// RGMII0_TXC (PIN_INPUT | MUX_MODE14) /* 0x250 */
// RGMII0_TXCTL (PIN_INPUT | MUX_MODE14) /* 0x254 */
RGMII0_TXD3 (PIN_INPUT | MUX_MODE14) /* 0x258 */
RGMII0_TXD2 (PIN_INPUT | MUX_MODE14) /* 0x25C */
RGMII0_TXD1 (PIN_INPUT | MUX_MODE14) /* 0x260 */
RGMII0_TXD0 (PIN_INPUT | MUX_MODE14) /* 0x264 */
// RGMII0_RXC (PIN_INPUT | MUX_MODE14) /* 0x268 */
// RGMII0_RXCTL (PIN_INPUT | MUX_MODE14) /* 0x26C */
// RGMII0_RXD3 (PIN_INPUT | MUX_MODE14) /* 0x270 */
// RGMII0_RXD2 (PIN_INPUT | MUX_MODE14) /* 0x274 */
RGMII0_RXD1 (PIN_INPUT | MUX_MODE14) /* 0x278 */
RGMII0_RXD0 (PIN_INPUT | MUX_MODE14) /* 0x27C */
USB1_DRVVBUS (PIN_INPUT | MUX_MODE14) /* 0x280 */
USB2_DRVVBUS (PIN_INPUT | MUX_MODE14) /* 0x284 */
GPIO6_14 (PIN_INPUT | MUX_MODE14) /* 0x288 */
GPIO6_15 (PIN_INPUT | MUX_MODE14) /* 0x28C */
GPIO6_16 (PIN_INPUT | MUX_MODE14) /* 0x290 */
XREF_CLK0 (PIN_INPUT | MUX_MODE14) /* 0x294 */
XREF_CLK1 (PIN_INPUT | MUX_MODE14) /* 0x298 */
XREF_CLK2 (PIN_INPUT | MUX_MODE14) /* 0x29C */
XREF_CLK3 (PIN_INPUT | MUX_MODE14) /* 0x2A0 */
MCASP1_ACLKX (PIN_INPUT | MUX_MODE14) /* 0x2A4 */
MCASP1_FSX (PIN_INPUT | MUX_MODE14) /* 0x2A8 */
MCASP1_ACLKR (PIN_INPUT | MUX_MODE14) /* 0x2AC */
MCASP1_FSR (PIN_INPUT | MUX_MODE14) /* 0x2B0 */
//MCASP1_AXR0 (PIN_INPUT | MUX_MODE14) /* 0x2B4 */
//MCASP1_AXR1 (PIN_INPUT | MUX_MODE14) /* 0x2B8 */
MCASP1_AXR2 (PIN_INPUT | MUX_MODE14) /* 0x2BC */
MCASP1_AXR3 (PIN_INPUT | MUX_MODE14) /* 0x2C0 */
MCASP1_AXR4 (PIN_INPUT | MUX_MODE14) /* 0x2C4 */
MCASP1_AXR5 (PIN_INPUT | MUX_MODE14) /* 0x2C8 */
MCASP1_AXR6 (PIN_INPUT | MUX_MODE14) /* 0x2CC */
MCASP1_AXR7 (PIN_INPUT | MUX_MODE14) /* 0x2D0 */
MCASP1_AXR8 (PIN_INPUT | MUX_MODE14) /* 0x2D4 */
MCASP1_AXR9 (PIN_INPUT | MUX_MODE14) /* 0x2D8 */
MCASP1_AXR10 (PIN_INPUT | MUX_MODE14) /* 0x2DC */
MCASP1_AXR11 (PIN_INPUT | MUX_MODE14) /* 0x2E0 */
MCASP1_AXR12 (PIN_INPUT | MUX_MODE14) /* 0x2E4 */
MCASP1_AXR13 (PIN_INPUT | MUX_MODE14) /* 0x2E8 */
MCASP1_AXR14 (PIN_INPUT | MUX_MODE14) /* 0x2EC */
MCASP1_AXR15 (PIN_INPUT | MUX_MODE14) /* 0x2F0 */
MCASP2_AXR2 (PIN_INPUT | MUX_MODE14) /* 0x30C */
MCASP2_AXR3 (PIN_INPUT | MUX_MODE14) /* 0x310 */
MCASP2_AXR4 (PIN_INPUT | MUX_MODE14) /* 0x314 */
MCASP2_AXR5 (PIN_INPUT | MUX_MODE14) /* 0x318 */
MCASP2_AXR6 (PIN_INPUT | MUX_MODE14) /* 0x31C */
MCASP2_AXR7 (PIN_INPUT | MUX_MODE14) /* 0x320 */
MCASP3_ACLKX (PIN_INPUT | MUX_MODE14) /* 0x324 */
MCASP3_FSX (PIN_INPUT | MUX_MODE14) /* 0x328 */
//MMC1_CLK (PIN_INPUT | MUX_MODE14) /* 0x354 */
//MMC1_CMD (PIN_INPUT | MUX_MODE14) /* 0x358 */
//MMC1_DAT0 (PIN_INPUT | MUX_MODE14) /* 0x35C */
//MMC1_DAT1 (PIN_INPUT | MUX_MODE14) /* 0x360 */
//MMC1_DAT2 (PIN_INPUT | MUX_MODE14) /* 0x364 */
//MMC1_DAT3 (PIN_INPUT | MUX_MODE14) /* 0x368 */
//MMC1_SDCD (PIN_INPUT | MUX_MODE14) /* 0x36C */
//MMC1_SDWP (PIN_INPUT | MUX_MODE14) /* 0x370 */
//ulpi
//GPIO6_10 (PIN_INPUT | MUX_MODE14) /* 0x374 */
//GPIO6_11 (PIN_INPUT | MUX_MODE14) /* 0x378 */
//MMC3_CLK (PIN_INPUT | MUX_MODE14) /* 0x37C */
//MMC3_CMD (PIN_INPUT | MUX_MODE14) /* 0x380 */
//MMC3_DAT0 (PIN_INPUT | MUX_MODE14) /* 0x384 */
//MMC3_DAT1 (PIN_INPUT | MUX_MODE14) /* 0x388 */
//MMC3_DAT2 (PIN_INPUT | MUX_MODE14) /* 0x38C */
//MMC3_DAT3 (PIN_INPUT | MUX_MODE14) /* 0x390 */
//MMC3_DAT4 (PIN_INPUT | MUX_MODE14) /* 0x394 */
//MMC3_DAT5 (PIN_INPUT | MUX_MODE14) /* 0x398 */
//MMC3_DAT6 (PIN_INPUT | MUX_MODE14) /* 0x39C */
//MMC3_DAT7 (PIN_INPUT | MUX_MODE14) /* 0x3A0 */
//SPI1_SCLK (PIN_INPUT | MUX_MODE14) /* 0x3A4 */
//SPI1_D1 (PIN_INPUT | MUX_MODE14) /* 0x3A8 */
//SPI1_D0 (PIN_INPUT | MUX_MODE14) /* 0x3AC */
//SPI1_CS0 (PIN_INPUT | MUX_MODE14) /* 0x3B0 */
//SPI1_CS1 (PIN_INPUT | MUX_MODE14) /* 0x3B4 */
SPI1_CS2 (PIN_INPUT | MUX_MODE14) /* 0x3B8 */
//SPI1_CS3 (PIN_INPUT | MUX_MODE14) /* 0x3BC */
//SPI2_SCLK (PIN_INPUT | MUX_MODE14) /* 0x3C0 */
//SPI2_D1 (PIN_INPUT | MUX_MODE14) /* 0x3C4 */
//SPI2_D0 (PIN_INPUT | MUX_MODE14) /* 0x3C8 */
//SPI2_CS0 (PIN_INPUT | MUX_MODE14) /* 0x3CC */
DCAN1_TX (PIN_INPUT | MUX_MODE14) /* 0x3D0 */
DCAN1_RX (PIN_INPUT | MUX_MODE14) /* 0x3D4 */
DCAN2_TX (PIN_INPUT | MUX_MODE14) /* 0x3D8 */
DCAN2_RX (PIN_INPUT | MUX_MODE14) /* 0x3DC */
UART1_RXD (PIN_INPUT | MUX_MODE14) /* 0x3E0 */
UART1_TXD (PIN_INPUT | MUX_MODE14) /* 0x3E4 */
//UART1_CTSN (PIN_INPUT | MUX_MODE14) /* 0x3E8 */
//UART1_RTSN (PIN_INPUT | MUX_MODE14) /* 0x3EC */
//UART2_RXD (PIN_INPUT | MUX_MODE14) /* 0x3F0 */
//UART2_TXD (PIN_INPUT | MUX_MODE14) /* 0x3F4 */
//UART2_CTSN (PIN_INPUT | MUX_MODE14) /* 0x3F8 */
//UART2_RTSN (PIN_INPUT | MUX_MODE14) /* 0x3FC */
WAKEUP0 (PIN_INPUT | MUX_MODE14) /* 0x418 */
WAKEUP1 (PIN_INPUT | MUX_MODE14) /* 0x41C */
WAKEUP2 (PIN_INPUT | MUX_MODE14) /* 0x420 */
WAKEUP3 (PIN_INPUT | MUX_MODE14) /* 0x424 */
TDI (PIN_INPUT | MUX_MODE14) /* 0x434 */
TDO (PIN_INPUT | MUX_MODE14) /* 0x438 */
TCLK (PIN_INPUT | MUX_MODE14) /* 0x43C */
TRSTN (PIN_INPUT | MUX_MODE14) /* 0x440 */
RTCK (PIN_INPUT | MUX_MODE14) /* 0x444 */
EMU2 (PIN_INPUT | MUX_MODE14) /* 0x450 */
EMU3 (PIN_INPUT | MUX_MODE14) /* 0x454 */
//===================================================================================
>;
};
uart3_pins_default: pinmux_uart3_pins {
pinctrl-single,pins = <
0x34c (PIN_INPUT | MUX_MODE4) /* mcasp5_axr0.uart3_rxd */
0x350 (PIN_OUTPUT | MUX_MODE4) /* mcasp5_axr1.uart3_txd */
>;
};
uart5_pins_default: pinmux_uart5_pins {
pinctrl-single,pins = <
VOUT1_D0 (WAKEUP_EN | PIN_INPUT | MUX_MODE2) /* vout1_d0.uart5_rxd */
VOUT1_D1 (PIN_OUTPUT | MUX_MODE2) /* vout1_d1.uart5_txd */
>;
};
uart6_pins_default: pinmux_uart6_pins {
pinctrl-single,pins = <
VOUT1_D8 (PIN_INPUT | MUX_MODE2) /* vout1_d8.uart6_rxd */
VOUT1_D9 (PIN_OUTPUT | MUX_MODE2) /* vout1_d9.uart6_txd */
VIN2A_D4 (PIN_OUTPUT | MUX_MODE8) /* vin2a_d4.uart6_ctsn */
VIN2A_D5 (PIN_INPUT | MUX_MODE8) /* vin2a_d5.uart6_rtsn */
>;
};
uart9_pins_default: pinmux_uart9_pins {
pinctrl-single,pins = <
MCASP5_ACLKX (PIN_INPUT | MUX_MODE8) /* mcasp5_aclkx.uart9_rxd */
MCASP5_FSX (PIN_OUTPUT | MUX_MODE3) /* mcasp5_fsx.uart9_txd */
>;
};
uart10_pins_default: pinmux_uart10_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT | MUX_MODE8) /* vin2a_d2.uart10_rxd */
0x174 (PIN_OUTPUT | MUX_MODE8) /* vin2a_d3.uart10_txd */
>;
};
mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_hs: pinmux_mmc1_hs_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.mmc1_clk */
0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
0x35C (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
>;
};
mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_clk.mmc1_clk */
0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
0x35C (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
>;
};
mmc1_pins_sdr104: pinmux_mmc1_sdr104_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.mmc1_clk */
0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
0x35C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
>;
};
mmc2_pins_hs: pinmux_mmc2_hs_pins {
pinctrl-single,pins = <
0x08C (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x090 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x094 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x098 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
0x09C (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0x0A0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0x0A4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0x0A8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0x0AC (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x0B0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
>;
};
mmc2_pins_ddr_1_8v: pinmux_mmc2_ddr_1_8v_pins {
pinctrl-single,pins = <
0x08C (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x090 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x094 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x098 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
0x09C (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0x0A0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0x0A4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0x0A8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0x0AC (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x0B0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
>;
};
mmc2_pins_hs200_1_8v: pinmux_mmc2_hs200_1_8v_pins {
pinctrl-single,pins = <
0x08C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x090 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x094 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x098 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
0x09C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0x0A0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0x0A4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0x0A8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0x0AC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x0B0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
>;
};
};
&dra7_iodelay_core {
mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
pinctrl-single,pins = <
0x620 (A_DELAY(560) | G_DELAY(365)) /* CFG_MMC1_CLK_OUT */
0x62C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
0x638 (A_DELAY(29) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
0x650 (A_DELAY(47) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
0x65C (A_DELAY(30) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
0x628 (A_DELAY(125) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
0x634 (A_DELAY(43) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
0x640 (A_DELAY(433) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
0x64C (A_DELAY(287) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
0x658 (A_DELAY(351) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
>;
};
mmc2_iodelay_hs200_1_8v_conf: mmc2_iodelay_hs200_1_8v_conf {
pinctrl-single,pins = <
0x194 (A_DELAY(150) | G_DELAY(95)) /* CFG_GPMC_A19_OUT */
0x1AC (A_DELAY(250) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
0x1B8 (A_DELAY(125) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
0x1C4 (A_DELAY(100) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
0x1D0 (A_DELAY(870) | G_DELAY(415)) /* CFG_GPMC_A23_OUT */
0x1DC (A_DELAY(30) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
0x1E8 (A_DELAY(200) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
0x1F4 (A_DELAY(200) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
0x368 (A_DELAY(240) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
0x190 (A_DELAY(695) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
0x1A8 (A_DELAY(924) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
0x1B4 (A_DELAY(719) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
0x1C0 (A_DELAY(824) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
0x1D8 (A_DELAY(877) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
0x1E4 (A_DELAY(446) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
0x1F0 (A_DELAY(847) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
0x1FC (A_DELAY(586) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
0x364 (A_DELAY(1039) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
>;
};
};
&i2c3 {
status = "okay";
clock-frequency = <400000>;
};
&i2c5 {
ov10633@37 {
compatible = "ovti,ov10633";
reg = <0x37>;
mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
port {
onboardLI: endpoint@0 {
remote-endpoint = <&vin2a>;
//hsync-active = <1>;
//vsync-active = <1>;
pclk-sample = <0>;
channels = <0>;
};
};
};
gpio_csi2_adap: tca6416@20 {
status = "okay";
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
ov490@24 {
compatible = "ovti,ov490";
reg = <0x24>;
mux-gpios = <&gpio_csi2_adap 0 GPIO_ACTIVE_LOW>,
/* CSI2_SEL_I2C_CLK */
<&gpio_csi2_adap 1 GPIO_ACTIVE_HIGH>,
/* CSI2_SEL_REF_CLK */
<&gpio_csi2_adap 3 GPIO_ACTIVE_HIGH>,
/* CSI2_CAM0_RESETn */
<&gpio_csi2_adap 4 GPIO_ACTIVE_LOW>;
/* CSI2_CAM0_PWR_DWN */
port {
csi2_cam0: endpoint@0 {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi2_phy0>;
};
};
};
};
&dss {
pinctrl-names = "default";
pinctrl-0 = <&vout3_pins>;
status = "ok";
vdda_video-supply = <&ldo5_reg>;
ports {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@lcd2 {
reg = <2>;
dpi2_out: endpoint {
remote-endpoint = <&lcd2_in>;
data-lines = <24>;
};
};
};
};
&hdmi {
vdda_video-supply = <&ldo5_reg>;
};
&pcf_gpio_21 {
interrupt-parent = <&gpio6>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
};
&mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_conf>;
};
&mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_1_8v>;
pinctrl-3 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_conf>;
};
// WNC
&uart1 {
/* use for GPIO declare */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
/* gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>; */
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_default>;
};
&uart5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart5_pins_default>;
};
&uart6 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart6_pins_default>;
};
&uart9 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart9_pins_default>;
};
&uart10 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart10_pins_default>;
};
&mac {
slaves = <1>;
mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii";
};
&ipu2 {
status = "okay";
memory-region = <&ipu2_cma_pool>;
};
&ipu1 {
status = "okay";
memory-region = <&ipu1_cma_pool>;
};
&dsp1 {
status = "okay";
memory-region = <&dsp1_cma_pool>;
};
&vip1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&vin2a_pins>;
vin2a: port@1 {
status = "okay";
};
};
video_in: &vin2a {
status = "okay";
endpoint@0 {
slave-mode;
remote-endpoint = <&onboardLI>;
};
};
&cal {
status = "okay";
};
&csi2_0 {
csi2_phy0: endpoint@0 {
slave-mode;
remote-endpoint = <&csi2_cam0>;
};
};
#include "dra7xx-jamr3.dtsi"
&tvp_5158{
status = "disabled";
mux-gpios = <&pcf_hdmi 2 GPIO_ACTIVE_LOW>, /*VIN2_S0*/
<&pcf_jamr3_21 8 GPIO_ACTIVE_LOW>, /*SEL_TVP_FPD*/
<&pcf_hdmi 6 GPIO_ACTIVE_HIGH>; /*VIN2_S2*/
};
/*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
/ {
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
aliases {
display0 = &hdmi0;
display1 = &lcd2;
sound0 = &snd0;
sound1 = &hdmi;
};
evm_3v3_sw: fixedregulator-evm_3v3 {
compatible = "regulator-fixed";
regulator-name = "evm_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
aic_dvdd: fixedregulator-aic_dvdd {
/* TPS77018DBVT */
compatible = "regulator-fixed";
regulator-name = "aic_dvdd";
vin-supply = <&evm_3v3_sw>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
evm_3v3_sd: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
};
#if 0
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
};
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
};
#endif
hdmi0: connector {
compatible = "hdmi-connector";
status = "disabled";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
tpd12s015: encoder {
compatible = "ti,tpd12s015";
status = "disabled";
gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
snd0: sound@0 {
compatible = "simple-audio-card";
simple-audio-card,name = "DRA7xx-EVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line Out",
"Microphone", "Mic Jack",
"Line", "Line In";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"MIC3L", "Mic Jack",
"MIC3R", "Mic Jack",
"Mic Jack", "Mic Bias",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
sound0_master: simple-audio-card,cpu {
sound-dai = <&mcasp3>;
system-clock-frequency = <11289600>;
};
simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
clocks = <&atl_clkin2_ck>;
};
};
#if 0
// GPIO5_8 is used for TDM pin
vmmcwl_fixed: fixedregulator-mmcwl {
compatible = "regulator-fixed";
regulator-name = "vmmcwl_fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
#endif
};
&dra7_pmx_core {
tps65917_pins_default: tps65917_pins_default {
pinctrl-single,pins = <
0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
>;
};
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc4_pins_default: mmc4_pins_default {
pinctrl-single,pins = <
0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
0x3fC (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
>;
};
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
>;
};
#if 0
// GPIO5_8 function in TDM
wlan_pins: pinmux_wlan_pins {
pinctrl-single,pins = <
0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
0x3fc (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
0x2cc (PIN_OUTPUT | MUX_MODE14) /* mcasp1_axr6.gpio5_8 - WLAN_EN */
>;
};
#endif
wlirq_pins: pinmux_wlirq_pins {
pinctrl-single,pins = <
0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */
>;
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
tps65917: tps65917@58 {
compatible = "ti,tps65917";
reg = <0x58>;
#if 0
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
#else
pinctrl-names = "default";
pinctrl-0 = <&tps65917_pins_default>;
interrupts-extended = <&gic GIC_SPI 2 IRQ_TYPE_NONE
&dra7_pmx_core 0x424>;
interrupt-parent = <&gic>;
#endif
interrupt-controller;
#interrupt-cells = <2>;
ti,system-power-controller;
tps65917_pmic {
compatible = "ti,tps65917-pmic";
tps65917_regulators: regulators {
smps1_reg: smps1 {
/* VDD_MPU */
regulator-name = "smps1";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps2_reg: smps2 {
/* VDD_CORE */
regulator-name = "smps2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
smps3_reg: smps3 {
/* VDD_GPU IVA DSPEVE */
regulator-name = "smps3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-boot-on;
regulator-always-on;
};
smps4_reg: smps4 {
/* VDDS1V8 */
regulator-name = "smps4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
smps5_reg: smps5 {
/* VDD_DDR */
regulator-name = "smps5";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
/* LDO1_OUT --> SDIO */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-allow-bypass;
};
ldo3_reg: ldo3 {
/* VDDA_1V8_PHY */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: ldo5 {
/* VDDA_1V8_PLL */
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* VDDA_3V_USB: VDDA_USBHS33 */
regulator-name = "ldo4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
};
tps65917_power_button {
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&tps65917>;
interrupts = <1 IRQ_TYPE_NONE>;
wakeup-source;
ti,palmas-long-press-seconds = <6>;
};
};
pcf_lcd: gpio@20 {
compatible = "nxp,pcf8575";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
pcf_gpio_21: gpio@21 {
compatible = "ti,pcf8575";
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
tlv320aic3106: tlv320aic3106@19 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x19>;
adc-settle-ms = <40>;
ai3x-micbias-vg = <1>; /* 2.0V */
status = "okay";
/* Regulators */
AVDD-supply = <&evm_3v3_sw>;
IOVDD-supply = <&evm_3v3_sw>;
DRVDD-supply = <&evm_3v3_sw>;
DVDD-supply = <&aic_dvdd>;
};
};
i2c_p3_exp: &i2c5 {
status = "okay";
clock-frequency = <400000>;
pcf_hdmi: pcf8575@26 {
compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
/*
* initial state is used here to keep the mdio interface
* selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
* VIN2_S0 driven high otherwise Ethernet stops working
* VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
*/
lines-initial-states = <0x0f2b>;
p1 {
/* vin6_sel_s0: high: VIN6, low: audio */
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "vin6_sel_s0";
};
};
};
&mcspi1 {
status = "okay";
ti,pindir-d0-out-d1-in;
spidev@0
{
spi-max-frequency = <100000>;
reg = <0>;
compatible = "rohm,dh2228fv";
status = "okay" ;
};
spidev@1
{
spi-max-frequency = <100000>;
reg = <1>;
compatible = "rohm,dh2228fv";
status = "okay" ;
};
spidev@3
{
spi-max-frequency = <100000>;
reg = <3>;
compatible = "rohm,dh2228fv";
status = "okay" ;
};
};
&mcspi2 {
status = "okay";
ti,pindir-d0-out-d1-in;
spidev@0
{
spi-max-frequency = <100000>;
reg = <0>;
compatible = "rohm,dh2228fv";
};
};
&mcspi3 {
status = "okay";
ti,pindir-d0-out-d1-in;
spidev@0
{
spi-max-frequency = <100000>;
reg = <0>;
compatible = "rohm,dh2228fv";
};
};
&uart1 {
status = "okay";
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<&dra7_pmx_core 0x3e0>;
};
&uart3 {
status = "okay";
gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
};
&elm {
status = "okay";
};
&gpmc {
/*
* For the existing IOdelay configuration via U-Boot we don't
* support NAND on dra72-evm. Keep it disabled. Enabling it
* requires a different configuration by U-Boot.
*/
status = "disabled";
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
* SW5.1 (NAND_SELn) = ON (LOW)
* SW5.9 (GPMC_WPN) = OFF (HIGH)
*/
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ /* device IO registers */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
gpmc,device-width = <2>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <80>;
gpmc,cs-wr-off-ns = <80>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <60>;
gpmc,adv-wr-off-ns = <60>;
gpmc,we-on-ns = <10>;
gpmc,we-off-ns = <50>;
gpmc,oe-on-ns = <4>;
gpmc,oe-off-ns = <40>;
gpmc,access-ns = <40>;
gpmc,wr-access-ns = <80>;
gpmc,rd-cycle-ns = <80>;
gpmc,wr-cycle-ns = <80>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000c0000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001c0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x001e0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00a00000 0x0f600000>;
};
};
};
&usb2_phy1 {
phy-supply = <&ldo4_reg>;
};
&usb2_phy2 {
phy-supply = <&ldo4_reg>;
};
&omap_dwc3_1 {
// extcon = <&extcon_usb1>;
};
&omap_dwc3_2 {
// extcon = <&extcon_usb2>;
};
&usb1 {
status = "ok";
dr_mode = "host";
};
&usb2 {
status = "ok";
dr_mode = "host";
};
&usb3 {
status = "disabled";
};
&mmc1 {
status = "okay";
vmmc-supply = <&evm_3v3_sw>;
vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is a viable alternative
*/
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
max-frequency = <192000000>;
};
&mmc2 {
/* SW5-3 in ON position */
status = "okay";
vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
ti,non-removable;
max-frequency = <192000000>;
};
&mmc4 {
#if 1
status = "okay";
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc4_pins_default>;
vmmc-supply = <&evm_3v3_sw>;
#else
status = "okay";
vmmc-supply = <&vmmcwl_fixed>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&wlan_pins &wlirq_pins>;
cap-power-off-card;
keep-power-in-suspend;
ti,non-removable;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@0 {
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
};
#endif
};
&mac {
status = "okay";
};
&dcan1 {
status = "ok";
};
&qspi {
status = "okay";
spi-max-frequency = <64000000>;
m25p80@0 {
compatible = "s25fl256s1";
spi-max-frequency = <64000000>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
/* MTD partition table.
* The ROM checks the first four physical blocks
* for a valid file to boot and the flash here is
* 64KiB block size.
*/
partition@0 {
label = "QSPI.SPL";
reg = <0x00000000 0x000040000>;
};
partition@1 {
label = "QSPI.u-boot";
reg = <0x00040000 0x00100000>;
};
partition@2 {
label = "QSPI.u-boot-spl-os";
reg = <0x00140000 0x00080000>;
};
partition@3 {
label = "QSPI.u-boot-env";
reg = <0x001c0000 0x00010000>;
};
partition@4 {
label = "QSPI.u-boot-env.backup1";
reg = <0x001d0000 0x0010000>;
};
partition@5 {
label = "QSPI.kernel";
reg = <0x001e0000 0x0800000>;
};
partition@6 {
label = "QSPI.file-system";
reg = <0x009e0000 0x01620000>;
};
};
};
&hdmi {
status = "disabled";
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};
&atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin1_ck>,
<&atl_clkin2_ck>;
assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
assigned-clock-rates = <0>, <0>, <180633600>, <361267200>,
<11289600>, <11289600>;
status = "disabled";
atl2 {
bws = <DRA7_ATL_WS_MCASP2_FSX>;
aws = <DRA7_ATL_WS_MCASP3_FSX>;
};
};
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializer */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
};
&mmu0_dsp1 {
status = "okay";
};
&mmu1_dsp1 {
status = "okay";
};
&mmu_ipu1 {
status = "okay";
};
&mmu_ipu2 {
status = "okay";
};
&ipu2 {
mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
timers = <&timer3>;
watchdog-timers = <&timer4>, <&timer9>;
};
&ipu1 {
mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
timers = <&timer11>;
watchdog-timers = <&timer7>, <&timer8>;
};
&dsp1 {
mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
timers = <&timer5>;
watchdog-timers = <&timer10>;
};
&oppdm_mpu {
vdd-supply = <&smps1_reg>;
};
&oppdm_core {
vdd-supply = <&smps2_reg>;
};
&oppdm_dspeve {
vdd-supply = <&smps3_reg>;
};
&oppdm_gpu {
vdd-supply = <&smps3_reg>;
};
&oppdm_ivahd {
vdd-supply = <&smps3_reg>;
};
/*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* Based on "omap4.dtsi"
*/
#include "dra7.dtsi"
/ {
compatible = "ti,dra722", "ti,dra72", "ti,dra7";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
/* cooling options */
cooling-min-level = <0>;
cooling-max-level = <2>;
#cooling-cells = <2>; /* min followed by max */
};
};
aliases {
rproc0 = &ipu1;
rproc1 = &ipu2;
rproc2 = &dsp1;
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupt-parent = <&wakeupgen>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
};
ocp {
cal: cal@4845b000 {
compatible = "ti,dra72-cal";
ti,hwmods = "cal";
reg = <0x4845B000 0x400>,
<0x4845B800 0x40>,
<0x4845B900 0x40>,
<0x4A002e94 0x4>;
reg-names = "cal_top",
"cal_rx_core0",
"cal_rx_core1",
"camerrx_control";
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
csi2_0: port@0 {
reg = <0>;
};
csi2_1: port@1 {
reg = <1>;
};
};
};
};
};
&scm {
dra72_vip_mux: pinmux@4a002e8c {
compatible = "pinctrl-single";
reg = <0xe8c 0x4>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
};
&dss {
reg = <0x58000000 0x80>,
<0x58004054 0x4>,
<0x58004300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1";
clocks = <&dss_dss_clk>,
<&dss_video1_clk>;
clock-names = "fck", "video1_clk";
};
&mailbox3 {
mbox_pru1_0: mbox_pru1_0 {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
status = "disabled";
};
mbox_pru1_1: mbox_pru1_1 {
ti,mbox-tx = <2 0 0>;
ti,mbox-rx = <3 0 0>;
status = "disabled";
};
};
&mailbox4 {
mbox_pru2_0: mbox_pru2_0 {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
status = "disabled";
};
mbox_pru2_1: mbox_pru2_1 {
ti,mbox-tx = <2 0 0>;
ti,mbox-rx = <3 0 0>;
status = "disabled";
};
};
&mailbox5 {
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
};
};
&mailbox6 {
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
};
BRs
Louis
