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Linux/DRA726: Could you please help me check DRA726 VIN1A input 24bits RGB method right or wrong?

Part Number: DRA726

Tool/software: Linux

Hi expert:

We are design J6-eco (DRA726) connect to VIN2A input 24bits RGB data to J6-eco.
Attached are the pin assign list and VIN1A schematic.
Now customer report that they just can input VIN1A_D8 - VIN1A_D23. All VIN1A_D0- VIN1A-D7 signal can not input to J6.
I have checked TRM Table 18-6. Customer configure CTRL_CORE_VIP_MUX_SELECT[6:4] VIP_SEL_1A bit set to 0x3.
They use VIP1A group4A pin mux. VIN1A_D8-VIN1A-D23 pin muxmod is 0x8.
But VIP1A_D0-VINP1A_D7 pin belong Group6A. CTRL_CORE_VIP_MUX_SELECT[6:4] VIP_SEL_1A can not set as Group4A and Group6A work at the same time.
I believe customer need change their schematic and use another interface of VIN1A_D0-D23 configure.
Their schematic connect of VIN1A_D0 ~ VIN1A_D7 is wriong.
Please help me check wehther my understand is right.
Best Regards!
Han Tao

Below are their pin mux configure and schematic.

  • Hi,

    I have pinged the experts to comment.

  • Hi Tao,

    Your assumption is right - Current configuration does not match any of the IOSETs.

    The I/O timings provided in DM are valid only for VIN1 and VIN2 if
    signals within a single IOSET are used. The IOSETs for VIN1 are defined in Table 7-4 of device DM.

    Note that depending on the use case needed, there are different IOSETs available - see Table 7-2. Modes Summary in device DM.

  • Hi Dian:

    Thanks for help us confirm it.

    DM table 7-4 compare with TRM Table 18-6 can give us a clear picture about pinmux connect and software setting.

    But i use PCT tool ( V1.3.0.9 and PCT_DRA72x_TDA2Ex23_v1.0.0.1), at VIN1A configure it did not have IOSET7.

    I suggest customer follow DM table 7-4 IOSET7 and use GROUP4A change VIN1A D0_D7 as below. PCT tool description  that those pin just have function VIN2A.

    Could you please check whether it is PCT tool wrong?

    DRA72x ES2.0 support DM tabel 7-4 (IOSET7 column)?

    B14 mcasp1_aclkr VIN1A_D0
    J14 mcasp1_fsr VIN1A_D1
    G13 mcasp1_axr2 VIN1A_D2
    J11 mcasp1_axr3 VIN1A_D3
    E12 mcasp1_axr4 VIN1A_D4
    F13 mcasp1_axr5 VIN1A_D5
    C12 mcasp1_axr6 VIN1A_D6
    D12 mcasp1_axr7 VIN1A_D7

    Best Regards!

    Han Tao

  • Hi Tao,

    Table 7-4. is correct - your suggestion for update is right.

    The team is now working on update for PCT that will fix this issue.

    Please note that VIN1A (IOSET7) requires usage of VIP_MANUAL1 (for Rise-Edge Capture Mode Timings) and VIP_MANUAL2 (for Fall-Edge Capture Mode Timings).

    This is included as an update in the upcoming version of both Data Manual and PCT.

  • Hi Dian:

    Thanks for help us clarify it.

    We will use new changed pin mux at VIP1 interface design the board.

    We will forget PCT tool configure at this version.

    Best Regards!

    Han Tao