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RTOS/OMAPL137-HT: Questions about SYSBIOS Cache Constants

Hoffiz
Expert 1670 points
Part Number: OMAPL137-HT
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Hi,

I'm trying to figure out a strange cache behavior.

#define Cache_Type_L1P ti_sysbios_family_c64p_Cache_Type_L1P
#define Cache_Type_L1D ti_sysbios_family_c64p_Cache_Type_L1D
#define Cache_Type_L1 ti_sysbios_family_c64p_Cache_Type_L1
#define Cache_Type_L2P ti_sysbios_family_c64p_Cache_Type_L2P
#define Cache_Type_L2D ti_sysbios_family_c64p_Cache_Type_L2D
#define Cache_Type_L2 ti_sysbios_family_c64p_Cache_Type_L2
#define Cache_Type_ALLP ti_sysbios_family_c64p_Cache_Type_ALLP
#define Cache_Type_ALLD ti_sysbios_family_c64p_Cache_Type_ALLD

If I do a call like:

Cache_wb(packeto[0], MAX_DATA*MAX_FRAMES, Cache_Type_ALLD, 1);

Will this write-back all data caches, all, or just the amount of bytes I selected from the set pointer for both in L2 DATA and L1 DATA ?

Jaime

  • 0
    Expert 1670 points

    A little more information, since I think handling cache coherence in my case should not be necessary. I have blocked some memory in the 128K between the ARM and DSP. So far my problems are not intercessors related as I'm testing on the DSP first. This memory area in in 0x80000000. I have a task that fills this buffer and then another task that calculates a crc on the written data. The task that fills this buffer is not a DMA.

    I guess I could move this buffer to the internal L2 RAM for testing. I have enabled 32k of L2 cache.

  • 0 in reply to Hoffiz
    TI__Guru 65405 points
    I've forwarded this to the TI RTOS experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0
    TI__Guru** 114410 points
    My understanding from the SYSBIOS document is that this API only does Writes back the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines within the range are left valid in the 'type' caches and the data within the range will be written back to the source memory.

    In addition to TI RTOS/SYSBIOS Cache APIs, you can also you device CSL cache APIs to perform the similar cache operations.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Expert 1670 points
    Thanks so what is the difference between the following constants. I found my issue, is not a cache problem, but I'm still not sure of the difference of these constants. The reason why I'm not sure is that at the end I still end up having to pass in the pointer to the start of the memory, so why would I have to speficfy L2D or ALLD.

    #define Cache_Type_L1P ti_sysbios_family_c64p_Cache_Type_L1P
    #define Cache_Type_L1D ti_sysbios_family_c64p_Cache_Type_L1D
    #define Cache_Type_L1 ti_sysbios_family_c64p_Cache_Type_L1
    #define Cache_Type_L2P ti_sysbios_family_c64p_Cache_Type_L2P
    #define Cache_Type_L2D ti_sysbios_family_c64p_Cache_Type_L2D
    #define Cache_Type_L2 ti_sysbios_family_c64p_Cache_Type_L2
    #define Cache_Type_ALLP ti_sysbios_family_c64p_Cache_Type_ALLP
    #define Cache_Type_ALLD ti_sysbios_family_c64p_Cache_Type_ALLD