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RTOS/TMS320C6657: Design question: data transfer to external FIFO through EMIF

Part Number: TMS320C6657
Other Parts Discussed in Thread: SN74AVC16T245, SN74V245, TMS320C6201

Tool/software: TI-RTOS

Hello

I would like to ask for advice regarding a design. The question contains some elements of software and some elements of hardware.

The idea is to transfer data to and from external FIFOs as outlined in

. Of course, the connection to the FIFOs (sn74v245) would succeed over voltage shifters (e.g. sn74avc16t245) but I do not think it will be a problem. My specific questions are:

0- That document was written for the tms320 family in general, and gives examples related to the 6201. Is it also valid for the 6657? Or what document(s) should I be reading?

1 - That document mentions EDMA transfers as a possibility. Is it actually possible to use EDMA transfers? I'm asking this question because I don't get to understand which DSP-pins I need to wire, or how do I setup the EMIF to generate/accept the right events during an EDMA transfer.

2- Should I consider using the uPP interface instead?

3- Are there any examples on similar hardware that I could use as a reference or starting point?

Thank you very much in advace!

Kind regards,

Pablo

PS. I've just tried to paste the URL of the document, it suceeded, but after a couple of seconds a big rectangle appeared. Hope you get a readable message.

  • Hi Pablo,

    I've forwarded your query to the experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • Hi Pablo,

    From a hardware perspective, using EDMA shouldn't be any different from using individual accesses. It will generate a string of accesses based on how you have configured the EMIF timing. The document you referenced appears to show a usable connection to a FIFO but you will need to check all the timing to be sure that setup and hold times are met for both parts. The selection of uPP vs EMIF is largely dependent on the data throughput you need. There are numerous posts discussing the throughput limitations of an EMIF interface. uPP provides better throughput but is a more difficult interface to design in. Unfortunately, we don't have any example designs connecting either uPP or EMIF to a FIFO that I can provide.

    Regards,

    Bill

  • Hello Bill

    thank you for your answer. I think I'll stick to EDMA, and I'll check the timings. I "believe" that I have the information for that. The quotations marks are there because the timings of the DSP-6657-EMIF16 are given in the revision B of the data sheet, and are not there in the revision C.

    There is still something I do not quite understand:

    Let's say I want to output data to a FIFO though the EMIF16. Then, at a certain point I would expect the DSP to generate an output signal (e.g. a rising flank) whenever some new data is ready to be traspased to the FIFO. However, when I read the documentation of the evaluation board TMDSEVM6657L, I read that those control pins (e.g. DSP_EMIFOEZ, DSP_EMIFWEZ, DSP_EMIFRNW) are only "input". Either I missunderstood something very basic, or is it a limitation of the evaluation board? In the first case I may have to set up a sync-mechanism for both the FIFO and the DSP, which somehow should be aware-of or synchronized-with the EDMA activity. In the latter case, what would be those signals generated by the EDMA activity that I could hook from?

    Equally confussing to me is that the EMIFA[23:0] and the CE[3:0] also are only "input". I'm starting to think that I missunderstood something very basic here. Any piece of advice will be highly appreciated.

    Thank you very much for your pacience.

    Kind regards,

    Pablo

  • Hi Pablo,
    The direction shown on the debug header in the schematic are relative to a board plugged into that connector. Address and command signals are inputs to a debug board.
    Regards,
    Bill
  • Hello Bill

    thank you for your prompt answer. I take it to mean that the documentation of the eval board only mentions one possible use (the debug board), and that other uses could exploit the full potential. Please correct me if I'm worng.

    Could you please point me to docs explaining what pins on the 6657 serve the asynchronous memory control of the TMS320C6201 ? I ask this question  because that is the DSP mentioned in the documentation that I referred to in my original question, and it makes extensive use of the ARE/AWE signals (shown on page 8 of ).

    Sorry that I'm a bit slow with these concepts, but I'm still strugling to understand what pins I should wire. In your first answer you say that it is possible to use EDMA, and there are older posts stating that, and only just that, but a fail to find the esential details in the docs. If I go for individual accesses I can of course provide the synchronism signals, but the whole thing would be too slow. If I go for EDMA then I need some hardware support from the DSP side, that could be connected to the RCLK/WCLK of the FIFO. But I fail to find exactly that information. Could you please point me to docs?

    Even if I think of an EDMA -> EMIF transfer of only one word, I need to signal the FIFO to accept the word _after_ it has been made available at the EMIF pins. May be I'm asking something so simple that you take for obvious.

    Kind regards,

    Pablo

  • Hi Pablo,
    Page 34 of the attached document shows the async memory access for the C6201. You can compare that with the diagrams on page 54 of the RevC C6657 datasheet. Remember that the EMIF interface is highly programmable so you will be able to change some of the timing parameters. For more information I suggest that you review the External Memory Interface (EMIF16) for KeyStone Devices User's Guide.

    You will find that the ARE and AWE on the C6201 corresponds with the EMIFOE and EMIFWE. (These are referred to as EM_OE and EM_WE in the diagrams. This is in the queue for correction.) An equivalent for AOE is not present in the EMIF16 interface. You would have to use some external logic to create an AOE signal when EMIFCEx is low and EMIFRW is high.

    Whether it's an EDMA or a single access, the EMIF will generate the signals shown in the timing diagram for every 16bit access (or eight bit access if you program it that way). The FIFO uses the RCLK to clock data in or WCLK to clock data out. You are using the OE and WE signals to clock the data. The rising edge of OE will clock data into the FIFO and the rising edge of WE will clock data out of the FIFO. As long as the setup and hold times are not violated, this should be possible.

    Don't get hung up on the EDMA aspect. EDMA is simply a method for moving large blocks from memory to the EMIF interrface without processor intervention. External to the part, these accesses all look the same.

    Regards,
    Bill
  • Thanks Bill for the very detailed answer. I've already spent a few hours on the documents you mention, but I could not get to relate ARE/AWE in the 6201 diagrams with EMIFOE/EMIFWE of the 6657. This information is key for me to understand the mechanism.