TMS320C5505: Urgent: Confirm the way to erase the Double buffer data on USB

Kaka

Hi TI Experts,

Please let me confirm the following question.
[Question]
Do you know the way to erase the data on double buffer on USB core?
My customer would like to know whether customer can erase the buffer data which they have already set in on USB core without sending any Garbage data to USB bus.
If yes, would please teach me the way to do?

Best regards.
Kaka

over 8 years ago

0 Yordan Kovachev over 8 years ago

TI__Guru**** 161600 points

Hi,
I've notified the team. Their feedback will be posted here.
Best Regards,
Yordan

0 Kaka over 8 years ago in reply to Yordan Kovachev

Guru 24520 points

Hi Yordan,

Thank you for your support.
I am waiting for your team response.

Best regards.
Kaka

0 Kaka over 8 years ago in reply to Yordan Kovachev

Guru 24520 points

Hi Yordan,

Do you have any updates for this topics?
We need to answer this question to our customer as soon as possible.

Best regards.
Kaka

0 Yordan Kovachev over 8 years ago in reply to Kaka

TI__Guru**** 161600 points

Sorry for the delay. We are looking into this.

Best Regards,
Yordan

0 Kaka over 8 years ago in reply to Yordan Kovachev

Guru 24520 points

I got it!! I am waiting for your response.

Best regards.
Kaka

0 Kaka over 8 years ago in reply to Kaka

Guru 24520 points

HI
Do you have any update for this topics??

Best regards.
KAKA

0 Kaka over 8 years ago in reply to Kaka

Guru 24520 points

Hi
I apologize for re-posting again. I am waiting for you feedback.

Best regards.
Kaka

0 Mukul Bhatnagar over 8 years ago in reply to Kaka

TI__Guru* 84485 points

Hi Kaka-san
Let me check internally on why we have not yet addressed this.
Sorry for the delay.
Will try to see if we can post an update to this thread tomorrow US time.

Regards
Mukul

0 Kaka over 8 years ago in reply to Mukul Bhatnagar

Guru 24520 points

Hi Mukul,

Thank you for your follow-up me.
I am waiting for your team feedback.

Best regards.
Kaka

0 Ming Wei over 8 years ago

TI__Guru 55665 points

Hi Kaka-san,

We have discussed this in the following thread:

e2e.ti.com/.../615996

Here is the summary again:

In order to clear the TX FIFO you have to do the following steps:

1. if FIFONOTEMPTY is 1 then set FLUSHFIFO to 1

2. check FIFONOTEMPTY again, if it is 1 then set FLUSHFIFO to 1 second time. You will only need to do this if double buffer is used and both buffers are filled and have not been transferred

3. if FIFONOTEMPTY is 0, then you are done

The above steps will clear any waiting data packet in the TX FIFO and the USB host will not get any garbage data.

Ming

0 Kaka over 8 years ago in reply to Ming Wei

Guru 24520 points

Hi Ming,

My customer have tried doing this sequence, but C5505 sent the Garbage data to USB bus. We would like to know "the way to erase the data on double buffer on USB core without any garbage data on USB bus". So, I re-asked the similar question to your team.

I and my customer thought the "FLUSHFIFO" means the "Clear the buffer on USB core". But I am thinking that the "FLUSH " means NOT the "clear the buffer", its the "Write the data to buffer and send the data".
So, would you please explain the function of FLUSHFIFO? And would you please show us the way to erase the data on double buffer on USB core without any garbage data on USB bus?

Best regards.
Kaka

0 Ming Wei over 8 years ago in reply to Kaka

TI__Guru 55665 points

Hi Kaka-san,

I think your customer's understanding about the FLUSHFIFO is correct. It means clear the data in the FIFO, because not only TX has that bit, the RX has it as well. There is another bit for the function you described in your post which is TXPKTRDY it informs the USB core that "the data has been written to the FIFO and ready to be sent out"

As of the garbage data on the USB bus during the FIFO clear, we will need more information. Can you share the customer code segment on the FIFO clear?

Best regards,

Ming

0 Kaka over 8 years ago in reply to Ming Wei

Guru 24520 points

Hi Ming,

Thank you for your comments. I will get customer's code.
By the way, do you have any sample code of this?

Best regards.
Kaka

0 Kaka over 8 years ago in reply to Kaka

Guru 24520 points

Hi Ming,

We got a question from my customer. So, please let me confirm the following question just in case.
[Question.1]
Is my understanding correct as below?
1. The next sent USB data is in FIFO(Double buffer).
2. Ready to send the data if the TXPKTRDY bit set by user .
3. FIFO data will transmit to CPU if requested by Host.

[Question.2]
Can it clear/erase the next USB data on FIFO by the FLUSHFIFO after set the TXPKTRDY?
i.e. On step 3 on above step, can it erase the FIFO(double buffer) data by using FLUSHFIFO before request from USB Host?

Best regards.
Kaka

0 Kaka over 8 years ago in reply to Kaka

Guru 24520 points

Hi Ming,

I would like to get your feedback as soon as possible.
Would you please provide your comments?

Best regards.
Kaka

0 Kaka over 8 years ago in reply to Kaka

Guru 24520 points

Hi

Could you please provide your answer by end of today in Japan time?

Best regards.
kaka

0 Ming Wei over 8 years ago in reply to Kaka

TI__Guru 55665 points

Hi Kaka-san,

I do not have example code for double buffering case. The following code section is from C55XCSL 3.07.00 csl_usbAux.h. It shows how to flush the EP FIFO. for double buffering case, you just need to repeat it one more time.

Ming

------------------------------------ Cut Here ----------------------------------------------------------

static inline
void USB_setConfiguration(CSL_UsbDevHandle hUsbDev,
Uint16 confVal)
{
Uint16 saveIndex;
Uint16 tempVal;

saveIndex = 0;

if(hUsbDev->devNum == CSL_USB0)
{
/* save the index register value */
saveIndex = usbRegisters->INDEX_TESTMODE;

  /* Configure EP1 for Tx and Rx */
  /* Select EP1 */
  usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
  usbRegisters->INDEX_TESTMODE |= CSL_USB_EP1;

  /* set ClrDataTog bit (TxCSR.D6) */
  usbRegisters->PERI_CSR0_INDX |= (CSL_USB_PERI_TXCSR_CLRDATATOG_MASK);
  /* set ClrDataTog bit (RxCSR.D7) */
  usbRegisters->PERI_RXCSR_INDX |= (CSL_USB_PERI_RXCSR_CLRDATATOG_MASK);

  /* Flush FIFO if not empty */
  if((usbRegisters->PERI_CSR0_INDX & CSL_USB_PERI_TXCSR_FIFONOTEMPTY_MASK) ==
     CSL_USB_PERI_TXCSR_FIFONOTEMPTY_MASK)
  {
   //usbRegisters->PERI_CSR0_INDX |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;

tempVal = usbRegisters->PERI_CSR0_INDX;

tempVal |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
tempVal &= ~(0x03);

usbRegisters->PERI_CSR0_INDX = tempVal;
}

  /* Configure EP2 for Tx and Rx */
  /* Select EP2 */
  usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
  usbRegisters->INDEX_TESTMODE |= CSL_USB_EP2;

tempVal = usbRegisters->PERI_CSR0_INDX;

tempVal |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
tempVal &= ~(0x03);

usbRegisters->PERI_CSR0_INDX = tempVal;
}

  /* Configure EP3 for Tx and Rx */
  /* Select EP3 */
  usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
  usbRegisters->INDEX_TESTMODE |= CSL_USB_EP3;

tempVal = usbRegisters->PERI_CSR0_INDX;

tempVal |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
tempVal &= ~(0x03);

usbRegisters->PERI_CSR0_INDX = tempVal;
}

  /* Configure EP4 for Tx and Rx */
  /* Select EP4 */
  usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
  usbRegisters->INDEX_TESTMODE |= CSL_USB_EP4;

tempVal = usbRegisters->PERI_CSR0_INDX;

tempVal |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
tempVal &= ~(0x03);

usbRegisters->PERI_CSR0_INDX = tempVal;
}

/* restore the index register */
usbRegisters->INDEX_TESTMODE = saveIndex;
}
}

0 Kaka over 8 years ago in reply to Ming Wei

Guru 24520 points

Hi Ming,

Thank you for your response.
How about my other question?

Best regards.
Kaka

0 Ming Wei over 8 years ago in reply to Kaka

TI__Guru 55665 points

Hi Kaka-san,

From C5515 TRM:
2.8.4.1.2 Operation
When data is to be transferred over a Bulk IN pipe, a data packet needs to be loaded into the FIFO and
the PERI_TXCSR register written to set the TXPKTRDY bit (bit 0). When the packet has been sent, the
TXPKTRDY bit will be cleared by the USB controller and an interrupt generated so that the next packet
can be loaded into the FIFO. If double packet buffering is enabled, then after the first packet has been
loaded and the TXPKTRDY bit set, the TXPKTRDY bit will immediately be cleared by the USB controller
and an interrupt generated so that a second packet can be loaded into the FIFO. The software should
operate in the same way, loading a packet when it receives an interrupt, regardless of whether double
packet buffering is enabled or not.

Q1: Here is the correct order for TX (USB IN):
1. It is very important that the next sent USB data has to be copied into the TX FIFO before the IN token
from the USB host comes in (for single or double buffer). If the IN token comes in and there is not data
in TX FIFO, the USB core will return NOT-YET.
2. After user copies the next sent data to the TX FIFO, then set the TXPKTRDY to 1, it will be cleared by the
USB core after the data has been transferred to the USB host or double buffer is used and user just loaded
the first of the double buffer in TX FIFO
3. When the IN token from the USB host is received by USB device (C55xx), USB device will start transfer the
data from the TX FIFO to the USB host (PC, Mac or Linux)

Q2: Yes, but it has to be in the step 2. Once the step 3 starts (when the In token arrives), you cannot flush the currently
transferring packet. As of the second buffer in the TX FIFO when double buffer is used, I am not sure the
FIFOFLUSH is going to behave. It maybe will clear the second buffer.

Best regards,

Ming

0 Kaka over 8 years ago in reply to Ming Wei

Guru 24520 points

Hi Ming,

Thank you for your kind response. But they have some questions again.

There is not the "NOT-YET" packet for IN token. The NOT-YET packet should be for OUT Token.Is my understanding correct ?

Also, they have used the Isochronous mode in order to send the audio data. In this mode, it does not use the handshake packet. Riht?

Do you have evaluate the operation of FLUSHFIO in case of using the Isochronous mode?

Best regards.

Kaka

0 Ming Wei over 8 years ago in reply to Kaka

TI__Guru 55665 points

Hi Kaka-san,

You are correct. It is not "NOT-YET". It should "NAK" when the USB host send the IN token while the USB device does not have the data ready to be sent.

As of the Isochronos mode, there is not acknowledge stage, but it still have IN tokens (or OUT token), therefore the procedure I expalined in the previous post about FLUSHFIFO stays the same. In fact, the acknowledge stage should be the step 4: USB host sends an "ACK" after receives the IN data. Since your customer is using the Isochronous mode, the step 4 does not exist.

Best regards,

Ming

0 Ming Wei over 8 years ago in reply to Ming Wei

TI__Guru 55665 points

Hi Kaka-san,

Can you share the customer's use case and explain why them need to flush FIFO?

In the case of USB audio class, the difficult part to understand is the initial TX FIFO setup. Here is how I implemented it:

1. Set up the EP IN to isochronous mode

2. Send an all-zero audio data packet to TX FIFO (size is determined by the number of channels and the sampling frequency)

3. Set the TXPKTRDY to 1, then wait for the TX EP interrupt to happen

4. The TX EP interrupt will occur when the data in the TX FIFO has been sent out to the USB host

5. In responding to the TX EP interrupt, put the next audio data packet (from Audio Codec input) to TX FIFO

6. Set the TXPKTRDY to 1

Repeat 4-6 as needed.

As you can see, there is no need for the FLUSHFIFO.

The only place I can see that you may need FLUSHFIFO is when you reset the EP or when you start the next cycle of the IN data sequence (starting from step 2 for second time). There may be a left over from last IN data sequence.

2 (modified): if (FIFONOTEMPTY ==1), set FLUSHFIFO to 1 (may need to it twice, if double buffer is used); Send an all-zero audio data packet to TX FIFO (size is determined by the number of channels and the sampling frequency).

Everything else stays the same.

Ming

0 Kaka over 8 years ago in reply to Ming Wei

Guru 24520 points

Hi Ming,

Thank you for your response. But, I am confuse for your answer.
The following is your previous Answer.

> Q1: Here is the correct order for TX (USB IN):
>1. It is very important that the next sent USB data has to be copied into the TX FIFO before the IN token
>from the USB host comes in (for single or double buffer). If the IN token comes in and there is not data
> in TX FIFO, the USB core will return NOT-YET.

It seems that there is the "NOT-YET" packet in IN token. And would you please answer for the following question?
> Do you have evaluate the operation of FLUSHFIO in case of using the Isochronous mode?
According to your answer, it seems that the answer is not. Right?

Best regards.
Kaka

0 Kaka over 8 years ago in reply to Ming Wei

Guru 24520 points

Hi Ming,

I will check the background to use the FLUSHFIFO.
If I get their feedback, I will post it.

Best regards.
Kaka

0 Kaka over 8 years ago in reply to Kaka

Guru 24520 points

Hi Ming,

I got their code and background for using the FLUSHFIFO from my customer.

[Background to use the FLUSHFIFO]
The reason why there is data remaining in the FIFO when the USB audio is opened since the end of the last communication is as below.
USB device needs to be loaded in advance due to the nature of USB protocol and there is a case that the "IN-TOKEN" do not sent from USB HOST until to get the last data. As a result, if FIFOFlush can not be done, the data of the previous butt will flow in the packet immediately after opening and become noise. This is why they would like to use the FLASHFIFO.

As you have thought, they would like to erase the FIFO before starting the Step.2 on you previous post in order to clear the previous packet data.
> 2. Send an all-zero audio data packet to TX FIFO (size is determined by the number of channels and the sampling frequency)

Their code is as below. Would you please checked whether there is any problem for it?
Note: I got feedback that they could not get the expected behavior even though use this.
****************
#define TX_EP (1)
void UsbAudioTxOpen()
{
int i;
volatile Uint16 reg;
for(i=0;i<2;i++)
{
reg = usbRegisters->EPCSR[TX_EP-1].PERI_TXCSR;
if ( reg & CSL_USB_PERI_TXCSR_FIFONOTEMPTY_MASK )
{
reg |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
reg &= ~(0x3);
usbRegisters->EPCSR[TX_EP-1].PERI_TXCSR; = reg;
}
}
reg = usbRegisters->EPCSR[TX_EP-1].PERI_TXCSR;
for(I=0;i<48*2;i++) usbRegisters->FIFO1R1 = 0;
usbRegisters->EPCSR[TX_EP-1].PERI_TXCSR = reg | CSL_USB_PERI_TXCSR_TXPKTRDY_MASK;
for(I=0;i<48*2;i++) usbRegisters->FIFO1R1 = 0;
usbRegisters->EPCSR[TX_EP-1].PERI_TXCSR = reg | CSL_USB_PERI_TXCSR_TXPKTRDY_MASK;
}
**************************

If you have any questions, please let me know.
Best regards.
Kaka

0 Ming Wei over 8 years ago in reply to Kaka

TI__Guru 55665 points

Hi Kaka-san,

What I was trying to tell you in the previous post is that when the IN token is coming from the USB host, if there is not data in the TX FIFO, then the NAK (my mistake, not NOT-YET) will be issued by the USB core to the USB host. That is why you will need to put the TX data in the TX FIFO before the IN token arrives.

Yes, we have verified the FLUSHFIFO in the double buffer case in the USB audio class 2.0 framework.

Ming

0 Ming Wei over 8 years ago in reply to Kaka

TI__Guru 55665 points

Hi Kaka-san,

The customer code about the FLUSHFIFO in the double buffer case looks OK. The only thing is that with this implementation there will be 2ms silence before the actual audio, but it seems un-avoidable because of the double buffering.

Ming

0 Kaka over 8 years ago in reply to Ming Wei

Guru 24520 points

Hi Ming,

Thank you for your comments.

But as I have written in previous post, my customer could not confirm the expected behavior if they using this code. i.e. C5505 send the garbage data to host even though they used this code.
This is why we have asked you whether FLUSHFIO can be erase the data on FIFO after TXPKTRDY set.

By the way, where can we get the the USB audio class 2.0 framework? Does this mean as below?

Best regards.

Kaka

0 Ming Wei over 8 years ago in reply to Kaka

TI__Guru 55665 points

Hi Kaka-san,

I meant

http://ap-fpdsp-swapps.dal.design.ti.com/index.php/USB_Audio_Class_2.0

Best regards,

Ming

0 Kaka over 8 years ago in reply to Ming Wei

Guru 24520 points

Hi Ming,

I could not access this URL.... Would you please double check whether non-TIer can access this?

Best regards.
Kaka

0 Kaka over 8 years ago in reply to Kaka

Guru 24520 points

Hi Ming,

Would you please answer for my question??

Best regards.

Kaka

0 Kaka over 8 years ago in reply to Kaka

Guru 24520 points

Hi Ming,

I am waiting for your feed back now.

Best regards.
Kaka

0 Ming Wei over 8 years ago in reply to Kaka

TI__Guru 55665 points

c55_usbac2_00_18_00_01.zipHi Kaka-san,

Attached please found the source code for the USB Audio Class 2.0 on C55xx.

Best regards,

Ming

0 Kaka over 8 years ago in reply to Ming Wei

Guru 24520 points

Hi Ming,

Thank you for your response.
I could get it. By the way, does this code modify to clear the double buffer ?
I checked this code, it seems that it does not implement .

Best regards.
Kaka

Processors

Processors forum

TMS320C5505: Urgent: Confirm the way to erase the Double buffer data on USB