RTOS/TMS320DM8148: reduce dsp power in the dm8148

Hi Shlomo,

You can use suspend/resume power management for the DSP (GEM) to reduce its power consumption when no audio processing is needed. Refer to the below wiki pages for more info:

processors.wiki.ti.com/.../TI81XX_PSP_User_Guide
processors.wiki.ti.com/.../TI81XX_PSP_PM_SUSPEND_RESUME_User_Guide
processors.wiki.ti.com/.../TI81XX_PSP_PM_FAQ

processors.wiki.ti.com/.../DM814x_AM387x_Power_Estimation

Regards,
Pavel

Hi Pavel

Thank you very much .
It will take me time to understand the subject so i will verify the answer .
Again , thanks ( - :

Hi Pavel ,

Sory but i need to know more .

I wrote a simple driver that write to these regs : ( based on the file Dm8168DspPwr.c )
CM_GEM_CLKSTCTRL , CM_ACTIVE_GEM_CLKCTRL , DSP_IDLE_CFG .

I manage to see that the dsp entered standby mode and out of 500 mili amper our device consume , a 15 miliamper was
droped . ( is that enough ?)

We nee to know : what happens to dsp clk when it enteres STANDBY mode ?
and if the clock does not drop to low where are it's relevant regs .

Can the dsp clock be managed in linux to save power ?

why the SPINBOX_CLKCTRL and MAILBOX_CLKCTRL are shut down in the dsp file ,
are they not used by all SoC modules ?

Can the dsp be powered Off ?

Regards .

Shlomo,

Shlomo Kabaz said:

I wrote a simple driver that write to these regs : ( based on the file Dm8168DspPwr.c )
CM_GEM_CLKSTCTRL , CM_ACTIVE_GEM_CLKCTRL , DSP_IDLE_CFG .

I manage to see that the dsp entered standby mode and out of 500 mili amper our device consume , a 15 miliamper was
droped . ( is that enough ?)

Make sure also DSP PLL is OFF (not locked). Check registers DSPPLL_CLKCTRL and DSPPLL_STATUS. Make sure CM_ACTIVE_GEM_CLKCTRL[1:0] MODULEMODE = 0x0, [17:16] IDLEST = 0x3, [18] STBYST = 0x1

Shlomo Kabaz said:

We nee to know : what happens to dsp clk when it enteres STANDBY mode ?
and if the clock does not drop to low where are it's relevant regs .

When DSP enters standby mode, dsp clock should be gated. You can check that in register CM_ACTIVE_GEM_CLKCTRL[1:0] MODULEMODE. When enter standby mode, this MODULEMODE value should switch from 0x2 to 0x0.

Shlomo Kabaz said:

Can the dsp clock be managed in linux to save power ?

Yes. This is fully explained in the links provided in my previous post.

Shlomo Kabaz said:

why the SPINBOX_CLKCTRL and MAILBOX_CLKCTRL are shut down in the dsp file ,
are they not used by all SoC modules ?

Spinlock and mailbox are not used by all the DM814x Soc modules, but only from Cortex-A8, DSP, Cortex-M3, HDVICP2. When power off DSP, if you still communicate between A8, M3 and HDVICP2 through spinlock/mailbox, you can leave their clock signals enabled.

Shlomo Kabaz said:

Can the dsp be powered Off ?

Yes, it can. Refer to the below e2e thread:

e2e.ti.com/.../937019

Regards,
Pavel

Hello Pavel ,

Thank you very much for your answer .

Still , after your explanation  it seems that  the mission is NOT  completed .

I  am writing this sequence :

reg =  __raw_readl( CTRL_MODULE_BASE_ADDR + DSP_IDLE_CFG);

reg &= 0xFFFFFFCF;

__raw_writel(  reg ,  CTRL_MODULE_BASE_ADDR + DSP_IDLE_CFG);

__raw_writel( 0x01 , PRCM_BASE_ADDR + CM_GEM_CLKSTCTRL);

__raw_writel( 0x01 , PRCM_BASE_ADDR + CM_ACTIVE_GEM_CLKCTRL);

 and  i read these values :

             CM_GEM_CLKSTCTRL: 0x00000601

   CM_ACTIVE_GEM_CLKCTRL: 0x00060002

                         DSP_IDLE_CFG : 0x00000008

                     DSPPLL_CLKCTRL: 0x281b0811

                       DSPPLL_STATUS: 0xc0000630

  Can you please tell me , what i did wrong or missed ?

Regards .

Shlomo,

Shlomo Kabaz said:

__raw_writel( 0x01 , PRCM_BASE_ADDR + CM_ACTIVE_GEM_CLKCTRL);

Shlomo Kabaz said:

CM_ACTIVE_GEM_CLKCTRL: 0x00060002

Why you write 0x1 in CM_ACTIVE_GEM_CLKCTRL register? The values allowed are 0x0 (disable clock) and 0x2 (enable clock). If your mission is to disable the DSP clock, write there 0x0, not 0x1.

Regards,
Pavel

Hi  Pavel ,

Thank you .

I  wrote this time 0  and it look better :

   in standby the regs are:

             CM_GEM_CLKSTCTRL: 0x00000001

   CM_ACTIVE_GEM_CLKCTRL: 0x00070000

                         DSP_IDLE_CFG : 0x00000000

   The current droped more .

   But the problem still exist when i try to get  out of standby and check the dsp status :

       to get out of standby i wrote :

            CM_GEM_CLKSTCTRL =  0x00000002

   CM_ACTIVE_GEM_CLKCTRL = 0x00000002

                         DSP_IDLE_CFG  = 0x00000028

   But the dsp stop responding !!!

   I was connected all the time with emulator  and it say that  the dsp is held in reset .

   What do i have to do in the dsp for that process to work .

   In my previuos arch , the  TI 5510 there was an "IDLE'  command , does we have it here also ?

    Should the dsp be in a function that resides in Internal RAM when going to standby mode ( now it does not )  ???

Regards .

 

Shlomo Kabaz said:

I  wrote this time 0  and it look better :

   in standby the regs are:

             CM_GEM_CLKSTCTRL: 0x00000001

   CM_ACTIVE_GEM_CLKCTRL: 0x00070000

                         DSP_IDLE_CFG : 0x00000000

   The current droped more .

   But the problem still exist when i try to get  out of standby and check the dsp status :

       to get out of standby i wrote :

            CM_GEM_CLKSTCTRL =  0x00000002

   CM_ACTIVE_GEM_CLKCTRL = 0x00000002

                         DSP_IDLE_CFG  = 0x00000028

   But the dsp stop responding !!!

Shlomo,

When using linux kernel, when using suspend/resume, you should not directly write into the DSP clock registers, this should be done by the suspend/resume functions.

When you want all the DM814x device to suspend (including DSP), you should execute the below command from user space:

$ echo -n "mem" > /sys/power/state

Then the below linux kernel function should disable the DSP clock during the suspend procedure:

ti814x_dsp_power_suspend() -> clk_disable(dsp_dev->ick), clk_disable(dsp_dev->fck)

Then when DM814x device wake up, it execute resume procedure:

ti814x_dsp_power_resume() -> clk_enable(dsp_dev->ick), clk_enable(dsp_dev->fck)

When you suspend the DSP (put in standby mode, disable clock), do you need the whole DM814x device to suspend (including the DSP) or you need only DSP to suspend?

Regards,
Pavel

Hi Pavel ,

Thank you .

We are not using this framework you were pointing .

I was instructed to put Only the dsp in standby .

We are using the DVRDK 04_01_00_02 , in it the framework for handling “suspend” is different from the
One you pointed .
In that env the “suspend” framework is in Syslink and build , among other , from the files:
ClockOps.c , Dm8168Clock.c , Dm8168DspPwr.c
We can not use now this framework !

From these files I am trying to understand the sequence for suspend/resume of Dsp .

Can you tell in what state the dsp has to be when we invoke it’s standby regs sequence ?

Should we change another regs for this process ?


Regards , Shlomo .

Shlomo,

Shlomo Kabaz said:

We are not using this framework you were pointing .

I was instructed to put Only the dsp in standby .

OK, that is feasible. You should change these PRCM registers from user space, with script or directly. Can you send me all your steps you are doing when you attempt to put the DSP in standby?

Shlomo Kabaz said:

We are using the DVRDK 04_01_00_02 , in it the framework for handling “suspend” is different from the
One you pointed .

I am not familiar with DVR RDK, I can not advice you regarding DVR RDK specific things. You can check with the TI network partners regarding DVR RDK support.

Shlomo Kabaz said:

Can you tell in what state the dsp has to be when we invoke it’s standby regs sequence ?

DSP should be in Active state before you invoke the standby procedure.

Shlomo Kabaz said:

Should we change another regs for this process ?

No, I do not think so. Please send me all you steps and the exact steps for review.

Regards,
Pavel

Hi  Pavel ,

right now i use only this sequence:

        To  put the DSP  in standby :

             reg =  __raw_readl( CTRL_MODULE_BASE_ADDR + DSP_IDLE_CFG);

            reg &= 0xFFFFFFCF;

           __raw_writel(  reg ,  CTRL_MODULE_BASE_ADDR + DSP_IDLE_CFG);

          __raw_writel( 0x01 , PRCM_BASE_ADDR + CM_GEM_CLKSTCTRL);

          __raw_writel( 0x00 , PRCM_BASE_ADDR + CM_ACTIVE_GEM_CLKCTRL);

 

      To  exit DSP from standby :

             reg =  __raw_readl( CTRL_MODULE_BASE_ADDR + DSP_IDLE_CFG);

            reg |= 0x00000028;

           __raw_writel(  reg ,  CTRL_MODULE_BASE_ADDR + DSP_IDLE_CFG);

          __raw_writel( 0x02 , PRCM_BASE_ADDR + CM_GEM_CLKSTCTRL);

          __raw_writel( 0x02 , PRCM_BASE_ADDR + CM_ACTIVE_GEM_CLKCTRL);

 Is that OK ?

 

Regards .

 

Shlomo Kabaz said:

   To  put the DSP  in standby :

Do you want to power OFF DSP completely or you just need to disable the DSP clock signals?

If you need just to disable DSP clock signals, you do not need to modify DSP_IDLE_CFG register. The first DSP clock is enabled/disabled by CM_ACTIVE_GEM_CLKCTRL and CM_GEM_CLKSTCTRL, the second one is controlled by the DSP PLL.

If you need to power off DSP completely, beside disable the clock signals, you should also modify DSP_IDLE_CFG register, RM_DEFAULT_RSTCTRL, PM_DEFAULT_PWRSTCTRL. This is explained in the e2e thread I have provided previously.

Regards,
Pavel

Hi Pavel ,

The sequence i invoke to enter dsp to STANDBY is :

reg = __raw_readl( CTRL_MODULE_BASE_ADDR + DSP_IDLE_CFG);
reg &= 0xFFFFFFCF;
__raw_writel( reg , CTRL_MODULE_BASE_ADDR + DSP_IDLE_CFG);
__raw_writel( 0x01 , PRCM_BASE_ADDR + CM_GEM_CLKSTCTRL);
__raw_writel( 0x00 , PRCM_BASE_ADDR + CM_ACTIVE_GEM_CLKCTRL);

and i read these values afterwards:

CM_GEM_CLKSTCTRL: 0x00000001
CM_ACTIVE_GEM_CLKCTRL: 0x00070000
DSP_IDLE_CFG : 0x00000008
DSPPLL_CLKCTRL: 0x281b0811
DSPPLL_STATUS: 0xc0000638
------------------------------------------

To step out of STANDBY I invoke:

reg = __raw_readl( CTRL_MODULE_BASE_ADDR + DSP_IDLE_CFG);
reg |= 0x00000028;
__raw_writel( reg , CTRL_MODULE_BASE_ADDR + DSP_IDLE_CFG);
__raw_writel( 0x02 , PRCM_BASE_ADDR + CM_GEM_CLKSTCTRL);
__raw_writel( 0x02 , PRCM_BASE_ADDR + CM_ACTIVE_GEM_CLKCTRL);

and i read these values afterwards:

CM_GEM_CLKSTCTRL: 0x00000702
CM_ACTIVE_GEM_CLKCTRL: 0x00000002
DSP_IDLE_CFG : 0x00000028
DSPPLL_CLKCTRL: 0x281b0811
DSPPLL_STATUS: 0xc0000638


What am i missing ?

Regards .

Shlomo Kabaz said:

What am i missing ?

You are missing to answer my question and to check my guidelines on my previous reply.

Regards,
Pavel

Hi Pave,

Thank you .. i did not see the last two posts .

We do need both options : "disabling totaly the dsp" and " saving power of dsp when ".

The second is the most important: After Dsp is up and functioning , we need to lower it's power as much as possible
and than using it again without loading it or restaring the sw ,
And from your post i understand that this should be doen by writing to :
CM_ACTIVE_GEM_CLKCTRL = 0x00
and CM_GEM_CLKSTCTRL = 0x01

but what should i write to the DSP PLL = can i reduce this clock while dsp is running .
We thought DSP PLL can be set only in u-boot and can not be changed when linux kernel is active or
after DSP is up ?

Regards .

Shlomo,

Try first with disable only the gem_ick, then enable it.

1. DSP is active and running, here we disable the iclk:

CM_GEM_CLKSTCTRL[1:0] CLKTRCTRL = 0x1
CM_ACTIVE_GEM_CLKCTRL[1:0] MODULEMODE = 0x0

Check here how the power consumption is impacted.

2. DSP is not-active, here we enable the ick again:

CM_GEM_CLKSTCTRL[1:0] CLKTRCTRL = 0x0
CM_ACTIVE_GEM_CLKCTRL[1:0] MODULEMODE = 0x2

First verify that you are able to disable and enable the dsp ick successful, then we can proceed with fck and then with power.

Regards,
Pavel

Hi Pavel ,

i did this sequence:
CM_GEM_CLKSTCTRL[1:0] CLKTRCTRL = 0x1
CM_ACTIVE_GEM_CLKCTRL[1:0] MODULEMODE = 0x0

I read the regs status now and they are:
CM_GEM_CLKSTCTRL: 0x701
CM_ACTIVE_GEM_CLKCTRL: 0x10000

But the dsp is running and power consumption is the same ( same current ) !!!

What now ?

Regards .

Shlomo Kabaz said:

i did this sequence:
CM_GEM_CLKSTCTRL[1:0] CLKTRCTRL = 0x1
CM_ACTIVE_GEM_CLKCTRL[1:0] MODULEMODE = 0x0

What were the values in these registers before you did that sequence?

Hi Pavel ,

The values were :
CM_GEM_CLKSTCTRL: 0x702
CM_ACTIVE_GEM_CLKCTRL: 0x2

Regards.

Shlomo,

Can you try the below sequence:

1. CM_GEM_CLKSTCTRL[1:0] CLKTRCTRL = 0x1
2. wait for 1 second
3. CM_ACTIVE_GEM_CLKCTRL[1:0] MODULEMODE = 0x0
4. wait for 1 second
5. read CM_GEM_CLKSTCTRL, CM_ACTIVE_GEM_CLKCTRL
6. check power consumption and current

Could you please also provide more details about "But the dsp is running"? What do you mean exactly? How do you check that DSP is running after MODULEMODE = 0x0?

Regards,
Pavel

Hi Pavel ,

After doing the above sequence i got:
CM_GEM_CLKSTCTRL: 0x701
CM_ACTIVE_GEM_CLKCTRL: 0x10000

In this state i tell the dsp from arm to print a list of msgs and it does .
I tell the dsp to print me every second a voaltiled counter that increments in my_idle_loop and
it is 94,000,000,000 as in regular operation mode .

Notice that the dsp is audio processing and rcvs interrupt from Tick sysbios , EDMA etz .

Regards.

Could you please provide the value of RM_ACTIVE_RSTCTRL register when DSP is active, before trying to stop the clock?

Try the below sequence:

1. CM_GEM_CLKSTCTRL[1:0] CLKTRCTRL = 0x1
2. wait for 1 second
3. CM_ACTIVE_GEM_CLKCTRL[1:0] MODULEMODE = 0x0
4. wait for 1 second
5. RM_ACTIVE_RSTCTRL = 0x3
6. wait for 1 second
7. read CM_GEM_CLKSTCTRL, CM_ACTIVE_GEM_CLKCTRL, RM_ACTIVE_RSTCTRL
8. check power consumption and current

Regards,
Pavel

Hi Pavel

Before i did the sequence you sugested regs are :
CM_GEM_CLKSTCTRL: 0x702
CM_ACTIVE_GEM_CLKCTRL: 0x2
RM_ACTIVE_RSTCTRL: 0

after acitaving the sequence:
CM_GEM_CLKSTCTRL: 0x700
CM_ACTIVE_GEM_CLKCTRL: 0x50000
RM_ACTIVE_RSTCTRL: 3

But , still , current is the same , did not change as for the power !!

Regards.

Shlomo Kabaz said:

CM_GEM_CLKSTCTRL: 0x700

Make sure you are writing 0x1 (not 0x0) in CM_GEM_CLKSTCTRL[1:0] CLKTRCTRL.

Try also the below sequence and report back if there will be any difference:

1. RM_ACTIVE_RSTCTRL = 0x3
2. wait for 1 second
3. CM_GEM_CLKSTCTRL[1:0] CLKTRCTRL = 0x1
4. wait for 1 second
5. CM_ACTIVE_GEM_CLKCTRL[1:0] MODULEMODE = 0x0
6. wait for 1 second
7. read CM_GEM_CLKSTCTRL, CM_ACTIVE_GEM_CLKCTRL, RM_ACTIVE_RSTCTRL
8. check power consumption and current

Regards,
Pavel

Hi Pavel

thank you for your answers .

this time i make sure that i am writing 0x01 to CM_GEM_CLKSTCTRL[1:0] CLKTRCTRL !

after acitaving the last sequence i got :
CM_GEM_CLKSTCTRL: 0x701
CM_ACTIVE_GEM_CLKCTRL: 0x50000
RM_ACTIVE_RSTCTRL: 3

still , current has not changed .

Can you please tell me what these registers should be after activating the sequence .

Can we also speak about the second dsp clock .


Regards .

Shlomo Kabaz said:

this time i make sure that i am writing 0x01 to CM_GEM_CLKSTCTRL[1:0] CLKTRCTRL !

after acitaving the last sequence i got :
CM_GEM_CLKSTCTRL: 0x701
CM_ACTIVE_GEM_CLKCTRL: 0x50000
RM_ACTIVE_RSTCTRL: 3

still , current has not changed .

Can you please tell me what these registers should be after activating the sequence .

CM_ACTIVE_GEM_CLKCTRL should be 0x70000. May be you should also modify DSP_IDLE_CFG in this sequence, the problem is that DSP_IDLE_CFG register is accessible only through supervisor/privilege level, thus not accessible from user space. This is discussed in the below e2e thread:

Shlomo Kabaz said:

Can we also speak about the second dsp clock .

You should disable DSP PLL, try the below sequence:

1. Check if PLLSS_MMR_LOCK register is configured to allow access to the PLL registers. Make sure you are writing the value of 517622845 (0x1EDA4C3D) in it before accessing the PLL registers.

2. Set DSPPLL_CLKCTRL[23] IDLE = 0x1

3. Wait till DSPPLL_STATUS[0] BYPASS == 1 and DSPPLL_STATUS[8] BYPASSACK == 1

4. Clear DSPPLL_CLKCTRL[0] TINITZ = 0x0

5. Set DSPPLL_PWRCTRL[0] OFFMODE = 0x1

6. Check DSPPLL_STATUS register, it should report PLL is not active (compare the value before that sequence, when DSP PLL is active and locked).

6.1 You can also check CM_ACTIVE_GEM_CLKCTRL register here

7. Check if DSP is still active, if still can process data

8. Check power consumption and current

Regards,
Pavel

Hi Pavel ,

Thank you for your answer .

I dont have problem now acessing registers since i am doing all now in the Kernel .
I tried again the DSP_IDLE_CFG , the current dropped in 20mili but i do not know how to go back to full power and operational Dsp ,
do you ?

I tried your sequence and it WORKED , it also dropped the current in 20 mili .

But the big succses was when i did PLL setting like in u-boot ( copied the code sequence from there ) and read one of your posts
telling there that lowering the DSP freq is doen by changing the DSP_M2 .

I lowered the dsp freq by dividing to 100 ( setting DSP_M2 = 100) and the current seem to drop again by 20 mili ,
and afterwards setting back the DSP pll freq to normal and all the system audio seem to be OK !!

Is this , for your opinion , a good method to handle dsp "sleep" power save .

Also , do you think i should power down the other "audio sub system elements" like Codec , Edma and McAsp ?


Regards , Shlomo.

Shlomo Kabaz said:

I tried again the DSP_IDLE_CFG , the current dropped in 20mili but i do not know how to go back to full power and operational Dsp ,
do you ?

Please provide the exact sequence you are doing to reduce the power and then to go back to full power, and I will have a look.

Shlomo Kabaz said:

But the big succses was when i did PLL setting like in u-boot ( copied the code sequence from there ) and read one of your posts
telling there that lowering the DSP freq is doen by changing the DSP_M2 .

I lowered the dsp freq by dividing to 100 ( setting DSP_M2 = 100) and the current seem to drop again by 20 mili ,
and afterwards setting back the DSP pll freq to normal and all the system audio seem to be OK !!

Is this , for your opinion , a good method to handle dsp "sleep" power save .

For DSP sleep power state, I think better solution is to gate off the DSP PLL clock completely (not just reducing the DSP PLL clock frequency).

Shlomo Kabaz said:

Also , do you think i should power down the other "audio sub system elements" like Codec , Edma and McAsp ?

It depends on your use case. If you power down these elements, you will get better power consumption, but will get higher latency when switching from full power to low power, and higher latency when switching from low power to full power.

Regards,
Pavel

Hi Pavel ,

Thank you for your answers .
I am sorry for the delay , we had urgent things and i was also seek .

I understood that when using the DSP_IDLE_CFG reg and inserting the DSP to StandBy , the dsp must have later on a reset ,
and that is not what we want , furthere more , the current drop at about 20 mili amper when the dsp enters Standby
and it is also the amount of current saved when i lower the DSP Pll or use the "Gate DSP PLL" sequence you showed me .

When i used your " Gate DSP Pll" sequence the current droped but the DSP still responds to comunication through syslink
( it works slower) . Is this OK ?

In our project , we do not need to use Video , only function a LCD .
What modules can be shut down when doing these function ( not using Videp actuallty) ?

Regards ,
Shlomo .

Shlomo Kabaz said:

When i used your " Gate DSP Pll" sequence the current droped but the DSP still responds to comunication through syslink
( it works slower) . Is this OK ?

DPLL_DSP is providing the functional clock to the DSP core. At that point (DPLL_DSP gated), you can check if you have the expected values in the below bits:

DSPPLL_PWRCTRL[0] OFFMODE = 1

DSPPLL_CLKCTRL[23] IDLE = 1

DSPPLL_STATUS[10] PHASELOCK = 0, [9] FREQLOCK = 0, [8] BYPASSACK = 1, [0] BYPASS = 1

CM_ACTIVE_GEM_CLKCTRL[1:0] MODULEMODE = 0, [17:16] IDLEST = 0x3, [18] STBYST = 1

Note that we have also interface (interconnect) (ick) (sysclk4) clock provided from DPLL_L3 to the DSP core. As this clock is still active, that might be the reason DSP core to respond through syslink.

Shlomo Kabaz said:

In our project , we do not need to use Video , only function a LCD .
What modules can be shut down when doing these function ( not using Videp actuallty) ?

This seems to me another issue, not related to the subject of this e2e thread. Please open new e2e thread regarding this issue with the corresponding subject.

Regards,
Pavel

Hi Pavel ,

This post and others of yours have been a great help for us .
We will come to this subject again in the future .

Have a good year !

Shlomo, Elbit systems - Israel .