I am using 4 chips of MT41K256M16TW each of them is 512MB. I am using a DM8147 processor.
2 chips of 512MB each uses memory controller 0. chipselect 0. So 1GByte is connected to memory controller 0 with chipselect 0.
2 chips of 512MB each uses memory controller 1 chipselect 1. So 1G Byte is connected to memory controller 1 with chipselect 1.
I wanted to check what registers need to be configured to support the above 2 GByte configuration. From the forums, I understand that LISA registers need to be programmed.
I wanted to find what are the correct values for SDRC_ADDR and SYS_ADDR bits. There are 4 LISA registers. Do i need to update all of them because i have 4 x 512MByte chips.
Could anyone share tested LISA register configurations for the above use-case.
Is it enough to update u-boot or do i also need to update kernel for this.
Thanks for your help.