Other Parts Discussed in Thread: ADS8471, DAC8820
Hi,
I have a customer developing an application to reads/write data in parallel with a C6655x DSP.
Please see below and provide helpful comments to the list of descriptions and answers to the questions.
Thanks in advance,
Simon
Description of the intended system:
- We want the device to download/upload tables from a computer using an USB connection. There are currently no high speed demands, so a USB-2 connection would work. Each table can be up to 40 Mbytes big. A latency of few seconds is more than enough. In the future, we may have the DSP to recompute the table, so much less information would need to be transmitted. Additionally, a USB-2 interface would immediately fit in the overall architecture.
- The tables are sequences of 16-bit values, which should be written to parallel DACs (DAC8820), or read from parallel ADCs (ADS8471). A rate of 1 MSa/s for each one of the DACs (minimum 2) and each one of the ADCs (minimum 2) should be achieved. That is a minimum rate of 2 MSa/s in each direction. Higher rates would be highly desirable, because they will allow more peripherals, or faster ones. The actual rate is not given by the DSP, but rather by an external trigger, and the resulting sampling is not evenly-spaced.
- We prefer parallel to serial because a serial transmission would mean a factor 4x16=64 higher frequencies (at least). Besides, parallel transfers over EMIF appear to have an upper bound of almost 70 MSa/s. Switching between external peripherals will imply intermediate latencies, but we have the impression that our 4 MSa/s requirement could be attained, and there will be room for extensions.
- We find it practical to add hardware FIFOs, and to setup the memory transfers as EDMA-transfers in order to comfortably meet the demands. Because no control loop is intended, the additional latencies do not affect the operation. Inspired by documents SPRA543 and SDMA003, we plan to work with FIFOs of the SN74V2x5 family. The FIFO works here as a buffer, the precise throughput requirements can be met by the (external) trigger circuitry, which actually triggers each DAC conversion using pre-latched values. With the proposed DAC/ADCs we achieve latencies of the order of a few nanoseconds.
- Due to possible extensions in the future, we are drawn to the c6000 family, using its EMIF-16 port. The cheapest member in that DSP family can probably do the job, and for the time being we will focus on that one. For the initial experiments we consider however the evaluation boards TMDSEVM6657L and TMDSEVM6678L (those “applications in the future” will involve a fair amount of floating-point computations).
Questions about the hardware design:
- We would like to have an XDS100 Emulator to be able to use CCS in connection to the DSP. We would also prefer the simplest possible design (without an external FPGA). Referring to the diagram of fig. 2.2 in document “/2016/04/C6657-Lite-EVM_TechnicalReferenceManual.pdf” our questions are:
- At first sight we thought that the orange elements were the key components of the emulator that we need to keep in the final design. However when looking at the schematics in “512992b2_xds100v3r_aug30_2011.pdf” we were not able to identify them. Can you please provide a block diagram of the DSP in combination with the XDS100 emulator?
- As we don’t intend to use any other emulation capability, we would replace all other components shown in fig. 2.2 with external passive logic. Would this hinder compatibility with CCS?
- Moreover we would like to know whether we need an additional FPGA, connected to the DSP, for the emulator to be able to work.
- Besides the USB connector for the emulator, we would like to have a second independent one. Can you please suggest an USB 2-controller and a communication channel (I²C, SPI, UART,…)? If there are schematics available serving a similar purpose they would be very helpful to us. A throughput of 20 MBytes/s and a latency of 1 s are enough.
- How can we deal with the boot configuration in order to leave as many GPIOs free as possible? We will need the GPIOs to control external logic.
