• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 4 answers
  • Subscribers 103 subscribers
  • Views 990 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2L06: Reference design applications?

Kenneth Witham
Intellectual 350 points
Part Number: 66AK2L06
Other Parts Discussed in Thread: RFSDK, DAC38J84, , ADC14X250

Hello,

I am currently looking at the following reference Design for the K2L: http://www.ti.com/tool/TIDEP0060

The user guide for this design (http://www.ti.com/lit/ug/tidub89/tidub89.pdf) references a Design Linux Application in section 6.3 of the document. I am wondering where I could find that application? Is it packaged inside the RFSDK? The user guide states to look under the design files for the reference design to get the software but the only design files listed on the page are schematics.

Thanks so much!

  • 0
    TI__Guru**** 161600 points
    I've notified the RFSDK team. They will post their feedback directly here.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Mastermind 37500 points
    Hello Kenneth,

    Hello,

    After RFSDK 2.00.06 the files for the 66AK2L06, and 14x250ADC, and DAC38J84 are included with the RFSDK.

    The files for programming the DAC38J84, ADC14x250 are discussed in www.ti.com/.../tidub94a.pdf
    The user guide and tool files are discussed in www.ti.com/.../tidub89.pdf, and www.ti.com/.../tidep0060

    a) 14x250 EVM - JESD ADC
    b) 66aK2L06 EVM - SOC with DFE, JESD, Serdes
    c) K2L HSP - Deterministic Latency Clock and JESD signal routing
    d) DAC38J84 EVM
    e) power splitter, ADC input filter, various cables and test equipment

    The K2L HSP Deterministic Latency Clock and JESD signal routing card - please contact 3rd party provider Azcom International

    Alternately, you can use the
    a) 14x250 EVM - JESD ADC - you need to provide the 245.76Msps ADC clock. The JESD serdes is 4.9152G
    b) 66aK2L06 EVM directly connected to the first JESD 0,1 port. You must have a rev2 or later EVM, or for rev1, there is a hardware modification.

    The ADC must be programmed prior to the RFSDK setup, and must have an active JESD serial output. You would download the Clock, ADC, and DAC GUIs and run these with the tidub94a.pdf configuration, before running the RFSDK portion.

    When you run the RFSDK you need to select the option for this use case from the GUI. This preselects the proper Linux setup files.

    Note: There is a JESD loopback example, this does not require the ADC hardware, it can be run from the 66AK2L06 EVM alone.

    Regards,
    Joe Quintal
  • 0 in reply to Radio-Joe
    Intellectual 350 points
    Perfect! Thank you so much. I was able to find the setup and have the radio turning on properly
  • 0 in reply to Radio-Joe
    Prodigy 65 points
    hello expert，66ak2l06 EVM rev2 or later its FMC jesd_clock pin constrait has been changed? TI.com can provide the changed schematic diagram?There is a label of my TCIEVMK2LX rev1.0.3.0.Is it belong to the rev 1? Can the RFSDK software change FMC clock pin constrait?
  • 0 in reply to user5273034
    TI__Mastermind 37500 points
    Hello,
    If you look in the TCIEVMK2LX _Technical_Reference_Manual.pdf Table 3-18, signal SYS_CLKP_FMC1 K4 is the SYSCLK for JESD.
    SYS_CLKN_FMC1 K5
    If you are asking if these signals can be moved to other traces. This is up to you, they only have 1 pair of locations on each of the 2 FMC connectors.

    If you are asking what the SYSCLK frequency is, other than 122.88Msps. This is an output from the EVM. If you are asking if an external SYSCLK can be used. There is a 10Mhz external clock input.

    If you are asking about SYSREF, there is a divided 122.88Mhz. The divider is programmable in the FPGA on the EVM.
    Again this is fixed on the connector J2 - SYSREF_P, and J3 - SYSREF_N.

    If you need to modify the above, to receive SYSCLK and SYSREF from an external source, that is EVM modification.

    Regards,
    Joe Quintal
  • 0 in reply to Radio-Joe
    Prodigy 65 points
    In 66ak2l06 evm the sysclk for JESD is K4 and K5，but in AD32RF80 the sysclk for jesd is d4 and d5.If the two evm connect directly, can the jesd work?I see some post,you have said they can work. Therefore I want ask some details?
  • 0 in reply to user5273034
    TI__Mastermind 37500 points
    Hello,
    The ADC EVM, may have its own CDC clock device, generating the 122.88Mhz, in which case the clock is asynchronous. This is not the best approach, but it has worked for some adjacent market designs. If you are trying to get determinisitic Latency Sub Category 1, you need to modify
    one board or the other, or generate an interposer card, that converts the 66AK2L06/TCI6630K2L to the desired data converter JESD connections:
    ADC - JESD Tx (usually at least 2 lanes) -> TCI EVM - JESD Rx (usually at least 2 lanes as 0,1 or 0,1,2,3)
    ADC - JESD Sync In (diff LVDS) <- TCI EVM - JESD Sync Out (diff LVDS)
    ADC - JESD SYSREF In (diff LVDS/ LVPECL) <- TCI EVM - Check EVM schematic, there is a modification for LvPECL, normally LVDS

    ADC - JESD SYSCLK In (diff LVDS / LvPECL) <- 122,88Mhz clock (clk has 10Mhz reference) -> TCI EVM (see EVM user Guide for external 10Mhz input clock)
    alternate method
    ADC - JESD SYSCLK In diff LVDS <- TCI EVM - JESD SYSCLK 122.88Mhz

    note: ADC SPI interface comes from USB to SPI adapter, and is controlled on PC. Look at 66Ak2L06 /32ADCRF80 design 4 guide.

    Regards
    Joe Quintal