DRA744: MII & RMII driver

In conjunction with schematics, I can see the following:

1. erratum number i903 - "50 Mhz output clock cannot meet RMII timings and should be used as input only" is not followed. This could cause a malfunction. Please consider one of the schematics shown on FIGURE 3-3 or FIGURE 3-4 in the PHY datasheet.

2. reset circuit (R1131 - C257) must be revised. This probably is not causing the malfunction but I see the following issues:

a) C257 = 10uF is directly connected to rstoutn pin and it is a considerable load. [because rstoutn already has few ms delay, consider much smaller C257]

b) since rstoutn pin is push-pull pin, the reset circuit isn't even performing it's purpose to delay the reset for about 50-100ms. The rstoutn buffer will try to charge and discharge the capacitor how fast it can, instead [add a diode from rstoutn pin to C257 isolate it from rstoutn = 1]

c) if it worked, it would unnecessary delay the other peripherals' resets on rstoutn pin [same diode will isolate back rstoutn from C257]

d) if it worked, it will not discharge C257 during power off, fast enough. I.e. reset circuit will not 'reset' itself. [a diode from C257 to 3V3 will discharge it faster during power off]

Please see figures 7-11 and 7-12 in PHY datasheet. Consider 1uF C257 instead.

I would personally also try to check if rstoutn delay is ok for PHY (>10 ms from PHY datasheet) and if true, then remove ALL components, and directly connect rstoutn to PHY RST#. This needs some research though.

Regards,

Stan

Hi Ho,

Ok, I see now. Still you need a diode from the capacitor to 3V3 to discharge it at power off or this circuit will not work properly whenever brief power outages occur.

I still would recommend to do a research if reset from SoC rstoutn is possible.

Regards,

Stan

It is more like this:

Diode will discharge the capacitor during power ramp down.