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AMIC110: DDR-less EtherCAT

Part Number: AMIC110
Other Parts Discussed in Thread: TIDEP-0105


Is it possible to implement DDR less EtherCAT application on AMIC110 without an external MCU or DDR?

The older ISDKs had example projects which runs only on the internal L2 cache. I do understand this ISDK is not supported now.
"Demonstrate DDR-less operation both with NOR XIP, SPI boot and using only the internal on-chip memory"

But the latest Processor SDK or the TI-Design (TIDEP-0105) mentions that we need to use an external MCU
to use AMIC110 without DDR.

Please let me know if it is possible to run EtherCAT on AMIC110 with Cache-Locking feature?
or this is not a supported feature?

If DDR or an External MCU is required, DDR+PMIC+AMIC110 would be too expensive solution for EtherCAT,
whereas other makers have inbuilt memory and less expensive power solution.

Best Regards

  • The RTOS team have been notified. They will respond here.
  • Hi Paddu, yes, it is possible to run EtherCAT slave on AMIC110 without DDR. We are about to release PRU-ICSS EtherCAT slave 1.0.6 (next few days) which makes easier to build and run DDR less application compared to our current 1.0.5 version.  If you want to give a try, I would suggest wait few more days until we have this version on

    thank you,


  • Hi Paula,

    Thank you for the information,
    glad to hear about the new EtherCAT slave SDK.

    Other than EtherCAT, is it possble to implement the same for other
    protocols like Ethernet/IP and Profinet?..Do we need DDRx for these protocols?

    Best Regards
  • Hi Paddu, different optimizations and strategies were done in order to convert EtherCAT slave to DDRless on AMIC110. Other protocols (such as Profinet, and EthernetIP) are bigger, so it would be really difficult to create a DDRless implementation on AMIC110. Other Sitara platforms, with bigger internal memory, could work, but we would need to do the analysis.

    thank you,