Other Parts Discussed in Thread: TIDEP-0105
Is it possible to implement DDR less EtherCAT application on AMIC110 without an external MCU or DDR?
The older ISDKs had example projects which runs only on the internal L2 cache. I do understand this ISDK is not supported now.
"Demonstrate DDR-less operation both with NOR XIP, SPI boot and using only the internal on-chip memory"
But the latest Processor SDK or the TI-Design (TIDEP-0105) mentions that we need to use an external MCU
to use AMIC110 without DDR.
Please let me know if it is possible to run EtherCAT on AMIC110 with Cache-Locking feature?
or this is not a supported feature?
If DDR or an External MCU is required, DDR+PMIC+AMIC110 would be too expensive solution for EtherCAT,
whereas other makers have inbuilt memory and less expensive power solution.