Other Parts Discussed in Thread: DS90UB954-Q1EVM
Hello all,
I am using the TDA2PXEVM together with the DS90UB954-Q1EVM and I have problems getting the setup to run with a CSI2 data rate of 800Mbps. Everything works fine for 400 Mbps, I am able to capture data and write it to the memory using the WRDMA of the CAL. The implementation is bare-metal. I am executing the CSI2 PHY Link initialization as per TRMv1.0, chapter 10.4.5.3. When PHY REG0/DS90UB954 are configured for a data rate of 800Mbps, then the STOPSTATE (point 2f of the init sequence) won't be reached and as a consequence the RESET_DONE of CAL_CSI2_COMPLEXIO_CFG will not be completed.
I am unsure if I configured the timings in REG0, REG1 of the PHY registers correctly:
For THS_TERM:
From the TRM: “Programmed value = floor(20 ns/DDR_CLK), where DDR_CLK is the period of the CSI-2 I/O lane rate. Default value: 4 (for 400 MHz).”
The default value is correct for a value of DDR_CLK=5ns (just looking at integer values), which would correspond to 200MHz. See questions at the end of the post.
For THS_SETTLE:
From the TRM: “Programmed value = floor(105 ns/DDR_CLK) + 4, where DDR_CLK is the period of the CSI-2 I/O lane rate. Default value: 39 (for 400 MHz).”
For the default value of 39, DDR_CLK would need to be between 3 and 3.0882, which corresponds to a value of around 333.3 MHz. See questions at the end of the post.
For TCLK_SETTLE:
From the TRM: “Programmed value = max[3, ceil(155 ns/CTRLCLK period) –1] Default value: 14 (for 96 MHz)”
The calculation is straight forward, though in the PDK the value is calculated by the following formula: “temp = (((Float32)260U / (Float32)DPHY_FUNCTIONAL_CLK_PERIOD) - (Float32)2U);”
This would mean a value of 22 instead of 14. See questions at the end of the post.
The calculation for TCLK_TERM is also different from what it is in the TRM, but in this case, both calculations lead to the same result.
For TCLK_DIV:
From the TRM: “Divide factor for CTRLCLK for CLKMISS detector Programmed value = ceil (15ns/CTRLCLK Period) – 1 Default value: 1 (for 96 MHz)
CLKMISS detection time = (5*TCLK_DIV+1)*(CTRLCLK period) < 60ns
Note: Only the CTRLCLK frequencies that satisfy above relationship are allowed. Typically, 96MHz will be used at CTRLCLK.”
Though with the default value of 1, the CLKMISS detection time is 62.5ns. See questions at the end of the post.
What was tested:
- Using either the period of the data rate or actual clock (half of data rate) for the calculations of THS_TERM, THS_SETTLE. I have been informed via E-Mail, that the data rate shall be used for these calculation. For a data rate of 800 MBit/s, the following values are calculated:
-
Using period of data rate (1.25ns) for calculation Using period of clock(2.5ns) for calculation THS_TERM floor(20ns/1.25ns) = 16 floor(20ns/2.5ns) = 8 THS_SETTLE floor(105ns/1.25ns)+4=84+4=88 floor(105ns/2.5ns)+4=42+4=46
- Using the PDK's calculation of TCLK_SETTLE, which leads to a value of 22 instead of 14, in combination with both the above values.
- Otherwise, standard values for TCLK_DIV(1) and TCLK_TERM(0) are used, for the standard control clock of 96MHz.
- Monitoring the CSI2 clock lane with an oscilloscope, output is 400MHz, which is expected for a data rate of 800Mbit/s.
Questions:
- Are there any other registers that have to be reprogrammed due to change in CSI2 data rate other than REG0 of the CSI2 PHY registers?
- To double check: Is it correct to use the period of the data rate for the calculations of THS_TERM, THS_SETTLE?
- For TCLK_SETTLE, TCLK_TERM: Should the calculations from the TRM or from the PDK be used?
- Is it ok for TCLK_DIV to not fullfill the "CLKMISS detection time <60ns" requirement with the aforementioned calculation?
Notes:
- File used from PDK (01_10_00_08) to compare the calculations: vpshal_calCsi2Tda2px.c
- Calculations for the above 5 parameters is the same in TRM(Nov17) for TDA2PX and TRM(June18) for TDA3
Thank you,
Regards,
Tobias
