AM5718: HDMI issue in certification due to HSW Horizontal Sync out of specs

Part Number: AM5718

Tool/software: Linux

Hi,

Our board with AM5718 ( Kernel 4.9 rt) has a HDMI output, we are trying to modify hdmi hsync width (HSW). I'm debugging  "/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c" in particular hdmi_core_video_config() function which seems to set all parameters regarding hdmi timing synchronization, specifically:

REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, (vm->hsync_len >> 8), 1, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, vm->hsync_len & 0xFF, 7, 0);

What happens is that any modification on vm->hsync_len seems not to have any effect on the HWS as measured by our instrument (Teledyne Lecroy 980).
May be this is not the correct place where to make this change ?

Hi, I will consult our Display Sub System driver expert and get back to you.

Regards,

Manisha

Hi,

I found that "void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, struct videomode *vm)" defined in ".../src/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c" is effective in changing hsw, acting on HDMI_WP_VIDEO_TIMING_H.
The strange thing is that this register should have address 0x5804 0068 and in TRM is described as RESERVED and only Read. Am I correct ? Anyway I succeded on changing hsw length ...

hdmi_wp_video_config_timing() already subtracts one from the videomode's hsw when programming to the register. Are you saying that you need to subtract two in total? Or is your platform somehow identified as OMAP4, on which "hsync_len_offset = 0"?

My TRM does not show the register reserved, but shows it containing the correct fields, and the address looks correct to me.

Which TRM are you referring to ? We have "SPRUHZ7H.pdf" where address  0x5804 0068 can be found only  in "Table 11-73. HDMI_WP Registers Mapping Summary"

whose Register Name is "RESERVED" and Type is "R" ...

The HDMI registers are described in a separate HDMI TRM, which is not available publicly.

HI Tom ,
writing in address 0x58040068 95 is generating a proper 96 pixel clock HSW .
writing in address 0x58040068 96 is generating a 97 pixel clock HSW .

customer was compiling , due to historical reason , linux kernel with OMAP_FB and the "old driver" puts 96 in the previous location .

compiling with OMAP_DRM option you get a 95 and everything works .

so question :
coudl you confirm a 95 in address 0x5804 0068 as per public datasheet is the correct operation to get 96 pixel clock HSW as we are measuring now ?

thank you
regards
Carlo