CCS/TMS320C6424: External DDR2 memory takes too much cycles for read and write

Hanan Kheiry

Part Number: TMS320C6424

Tool/software: Code Composer Studio

Hello everyone,

I'm working on optimizing a project , and I faced some time issues with some functions that include DDR2 read or write , those functions take too long time when its variables are placed in DDR2 , more than the number of cycles that it should takes for accessing DDR or perform read or write operation. what could be the reason for this issue ? ,and what the possible reasons that can slow down DDR2 and degrade its performance ?

Note :

- we have a problem with cache enabling so its disables for now.

- we are using BIOS 5_42_02_10 version.

Thanks in advance.

over 5 years ago

0 Yordan Kovachev over 5 years ago

TI__Guru**** 161600 points

Hi,

I've notified the team, but answers may be delayed due to holidays in the US.

Best Regards,
Yordan

0 Hanan Kheiry over 5 years ago in reply to Yordan Kovachev

Prodigy 90 points

the issue was resolved by reducing the amount of DDR space used , we noticed that when less than 55% of the memory (55% of the total size) is used the performance is good and it works as it should, but when it's more than 55% of the memory ,performance degradation shows up again. but we didn't realize whats is the relation between the amount of the memory used and its performance , can anyone justify this behavior ?!

0 Mark Mckeown over 5 years ago in reply to Hanan Kheiry

TI__Mastermind 29210 points

Hi,

I wonder if this throughput hit is related to the changing state of the bank address (BAn) signals. Or else maybe the cache.

Have you considered Usage Note 2.1.1 Bus Priority Inversion can Affect DDR2 Memory Controller Throughput in the TMS320C642x Silicon Errata SPRZ252D? www.ti.com/.../sprz252d.pdf

The DDR2 memory controller arbitration policy gives preference to accesses to open banks.

Are there multiple modules accessing DDR? Or is the behavior repeatable with a simple memory test? Are you using DMA?

Chapter 6 Bandwidth Management Architecture in the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871K) may offer some clues.
www.ti.com/.../spru871k.pdf

Hope this helps,
Mark

0 Brad Griffis over 5 years ago

TI__Guru*** 125430 points

Hanan Kheiry said:
- we have a problem with cache enabling so its disables for now.

If cache is disabled it will completely ruin your performance (around 100x worse). It is such a severe issue that I wrote an entire wiki page to help explain why it is so slow:

http://processors.wiki.ti.com/index.php/Common_Issue_Resulting_in_Slow_External_Memory_Performance

You need to make sure to:

Enable cache
Set the appropriate MAR bits

There's a wiki page for that too:

http://processors.wiki.ti.com/index.php/Enabling_64x%2B_Cache

Best regards,
Brad

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CCS/TMS320C6424: External DDR2 memory takes too much cycles for read and write