I have been doing extensive development on this part -- no RTOS --and am using the UART for debugging. Among the first things I got working was the UART. But recently it has begun to fail.
This is what happens.
I am prepared for an interrupt whenever the transmitter empties. When I feed a character to the UART0:THR register. The interrupt asserts. I have a breakpoint inside it, that is reliably hit, but after I step over or run through the HWREG(SOC_UART_0_REGS + UART_THR) instruction, no data appears in the register although the the IIR register flashes an interrupt pend which is cleared when the interrupt asserts again.
Does one of you geniuses recognize a familiar problem?
Here is the register file directly after a write to THR
UART0 UART
RBR 0x00000000 Receiver Bu
THR 0x00000000 Transmitt
IER 0x00000007 The neratedwarded to the CPU. [Memory Mapped]
IIR 0x000000C2 The interruenabled in the interrupt enable ry Mapped]
Reserved ************************ Reserved
FIFOEN 11 FIFOs Enabled Always 00b in Non-FIFO modthe FCR register is set
Reserved ** Reserved
INTID 001 - THRE Encodes the different types of interrupt
IPEND 0 - PEND Interrupt Pending This bit is us
FCR 0x000000C1 The FIFO control register (F trigger led. [Memory Mapped]
LCR 0x00000003 The system programmer controls the format of Memory Mapped]
MCR 0x00000000 The modem control register provides the ability to enable
LSR 0x00000060 LSR provides informationhrough [Memory Mapped]
MSR 0x00000001 Modem Status Register [Memory Mapped]
SCR 0x00000000 Scratch Pad Register [Memory Mapped]
DLL 0x00000036 DLL holds the least-signif
Any ideas?
