TMS320VC5401 HP1(GPIO),Uart Registers addressing Details

Ashwin,

The register addreeses for the 5401 registers are available in the spec sheet located here http://www.ti.com/lit/gpn/tms320vc5401.  See sections 3.9 through 3.12.

Note that the registers are memory mapped and not in I/O space.  The 5401 does contain an I/O space but it is only applicable to the external memory bus via the nIS select signal.

The memory mapped registers can be accessed just as you did before except the ioport modifier will not be used.

The McBSP and DMA registers are actually accessed through a portal style interface similar to an external peripheral through a serial port.  In this interface, you write a register address to one memory mapped register and read/write data through another memory mapped register.  This causes some small changes to the way you will define your access marcos for the McBSP and DMA control registers.  The data registers are accessed directly as before. 

Here is an example mechanism to access the McBSP0 XCR1 register behind the portal, other registers are defined similarly

#define SPSA0     ( *( volatile unsigned int * )0x38 )

#define PTR2SPSD0 ( ( volatile unsigned int *)0x39 )

#define XCR10     ( *( SPSA0 = 0x04, PTR2SPSD0 ) )

Note that the macros take advantage of the comma operator which returns the value of the last object in the comma list thus the macros can be used in any programming construct including if, while, and function calls.

One caveat of this style of macro is that multiple accesses to the same register will not optimize away the address write operation.  If you have time critical code where this needs to be handled differently you would do something like this

XCR10 |= 0x04;  // first access sets portal address too

*PTR2SPSD0 |= 0x80;  // second write to same register but omits redundant address update

Another thing to remember is that that if you do attach any external peripherals to the I/O bus, all accesses are hard coded into the machine instruction, i.e. there are no indirect accesses via register values as in the 55x DSP's.  The only way to accomplish this is to move a small function to RAM and have it modify the opcode before accessing the I/O space.  Note you will also need to provide enough NOP instructions (or other instructions) so the pipeline doesn't read the incorrect opcode before you actuallly update it.  I don't remember exactly how many this is but the number 6 seems to be in my mind as you need to take into account not only the pipline stages before the execution phase but also the write stages following it so the write is actually implemented.

Regards,

Jim