This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RTOS/TMS320C6727: EMIF ASYNC Memory and DSP/BIOS TSK Issues

Part Number: TMS320C6727

Tool/software: TI-RTOS

Hello,

I have a test program, that includes DSP/BIOS, for an in-house C6727 breadboard that we created. This test program runs simple tests on the external memory that we have connected through the EMIF, an SDRAM and NOR Flash. For example, one test is to simply write a value to every memory location in the specified memory and read it back to confirm. We've recently decided to test how long it takes to complete these tests, and I decided to accomplish this using the DSP/BIOS CLK module. To accomplish this, I had to move our test program from a while-loop in main into a while-loop in a DSP/BIOS TSK, otherwise the CLK module does not properly increment (since main() never returns). Once I moved the while-loop into the TSK, I started experiencing strange behavior with the ASYNC memory on the EMIF bus, removing the code from the TSK relieves this behavior. 

Before I continue, here's some information about the system:

  • C6727 DSP
  • Using CCS3.3 with compiler 6.0.8
  • DSP/BIOS 5.31.02

I was able to hook the EMIF bus up to a logic analyze and it appeared to be occasionally putting out random data on the EMIF bus with the ASYNC write-enable pin active, when there was no code writing the EMIF. It almost seems like using a TSK does something strange with the EMIF. When doing my NOR test that writes data to every memory location, it appears to fail at different moments, as if when the TSK switches it dies. Sometimes it will write 5 memory locations before going off in the weeds, sometimes it will write 100, or even 1000. But it does seem to fail every time.

One of the failures that occurs during the test is that the NOR flash will begin the erase sequence, which requires five very specific commands to be sent to the flash in a specific order. It's quite mind boggling why this might be happening, but I assure you, I am not sending the erase command. It's important to note that if I move the while-loop and the test into main() and never return from main, the NOR test runs perfectly fine. 

I do not seem to experience these problems when testing the SDRAM. 

Any help or information regarding what the DSP/BIOS TSKs do to the EMIF bus will be greatly appreciated.

Thank you,

Vincent Galbo