Hi,
I'm hoping to double-check how cache parity/ECC failures are reported as this is naturally difficult to test. My understanding is:
- To enable exceptions on L1 parity failures, I just need to set L1PE in the Auxiliary Control Register
- To enable exceptions on L2 parity or ECC failures, I just need to set "Parity or ECC enable" bit 21 in L2 Cache Auxiliary Control Register.
Are there any other steps needed to enable generation of exceptions?
And is there an easy way to test this, e.g. using the L2 parity/ECC array operations in CP15?
