TMS320C6726B: Performing SPI Master transfer over DMA (dMAX)

Hi Alec,

n looking at the datasheets for dMAX (SPRU795D) and SPI (SPRU718B), it's not clear to me whether the DMA supports an outbound transfer over SPI, with SPI set in the master mode.

Take a look at the SPI user guide (www.ti.com/.../spru718b.pdf ), section 7 DMA Interface:
The SPI supports a DMA interface for transmit and receive data transfers.

Later in the same document:

"To use the SPI DMA interface, the SPIINT0.DMAREQEN bit should be set to '1' and SPIINT0.RXINTEN should be set to '0'. The SPIINT0.DMAREQEN must be set to ‘1’ only after the SPIGCR1.ENABLE is set. If the SPIINT0.DMAREQEN is set before SPIGCR1.ENABLE is enabled then the first DMA request may be dropped.
The SPI will generate an active high request pulse when it is time to service the transmit and receive buffers.

On the C672x device, this request is routed to the dMAX unit:
• SPI0 request is routed to dMAX Event Input 13
• SPI1 request is routed to dMAX Event Input 14"

Best Regards,
Yordan

Hi Yordan,

Thanks for looking at this.  From what I understand, the language above refers to using SPI in slave mode -- that is, when a transfer is initiated by an external (master) device talking to the slave.

However, I want the DMA to automatically perform a sequence of writes over SPI (with SPI in master mode).  For example, provide the DMA with an address and size corresponding to a block of data to transfer over SPI, and then tell the DMA to 'go' while the processor is free to perform other functions.  Do you know if this is possible?

Thanks,

Alec

See reply below.

After looking at this again, I think what you have provided here may be enough information to perform the "SPI master" transfers. It looks like it may just require manually triggering the first SPI request event by setting the corresponding bit in the dMAX Event Flag Register (DEFR), after which the SPI master will automatically perform future DMA requests after SPI write.

At least I hope this is the case. It is opaque what causes the SPI to generate a request event. According to what you provided above, it's "when it is time to service the transmit and receive buffers". However, I'm not sure if that means it's due to, e.g., a SPI Rx buffer full flag being set, a chip select being disable, etc. I will try to test this out on hardware.

Slide 8 of this presentation shows the DMA/SPI configuration: www.ti.com.cn/.../spna105.pdf

Hi,

Sorry for the delay. Yes, SPI should be able to perform this when set in master mode. To see what triggers SPI to transfer data on the bus, take a look at Section 2.5 SPI Operation: 3-Pin Option & Section 2.6 SPI Operation: 4-Pin With Chip Select Option in the user guide (www.ti.com/.../spru718b.pdf).
I understand you use CS signal, so the transaction is triggered when the DSP has written transmit data to the SPIDAT0[15:0] or the SPIDAT1[15:0] register, but in master mode you have to toggle the CS first to select a slave.

Best Regards,
Yordan

Yordan,

Yes, we actually already have 5-pin SPI master mode working on it's own.  However, when it comes to using the DMA to transfer over SPI in master mode, it does not seem the DMA was designed to work this way.

As a workaround, I tried setting the SPI to 5-pin master mode, and then configuring the DMA for SPI (slave) mode.  I then manually write a value to the SPI register (SPIDAT0/1), in the hopes that after the master-configured SPI writes out the value, the returned value on the MISO bus will cause the SPI_DMA_REQ from SPI to DMA to pulse (see slide 8 from www.ti.com.cn/.../spna105.pdf).  However, so far this has not been working.  I am going through registers to verify everything was configured as expected, but I'm afraid that it is not possible to use SPI/DMA in this way.

Alec