TMS320VC5501: MCBSP setup and dma

Glenn Dahl

Part Number: TMS320VC5501
Other Parts Discussed in Thread: PCM3168A, SPRC133

I am having an issue with dma transfers. From memory to mcbsp. There are two channels. one works fine, the other occasionally has sync issues. Both have FS in the ACCR reg set to 0. Both have AUTOINIT set to on. The good one has SYNC_XEVT0 set. The bad one has SYNC_XEVT1. Oddly enough I only have Int0 being active externally to the dsp. Int1 isn't even connected. its just pulled up. I am picking this code up from an eng that is no longer here. So, how can the bad channel ever run if its waiting for a int1, which will never transition. Does autoinit being on affect the sync waiting for the external int? In other words, if autoinit is on, does checking int1 only matter for the first transfer?

over 5 years ago

0 Cvetolin Shulev-XID over 5 years ago

TI__Guru 65405 points

Hi Glenn,

Could you share your source code because it hard to me to comment what exactly happens.

Regards,
Tsvetolin Shulev

0 Glenn Dahl over 5 years ago in reply to Cvetolin Shulev-XID

Prodigy 100 points

without an nda I cant share the whole code base. And the original writer was hard to follow anyway. If you need more, let me know.

We essentially have two mcbsps running.the first one uses both transmit and receive. the second uses just transmit. Both go to codecs. PCM3168A. The problem we have is at startup only. And it doesn't happen everytime. The first mcbsp works fine, everytime. The second mcbsp will occasionally startup with its data shifted by what looks like 16 bit. This is also the odd part, that I havent understood yet. The dmas appear to be 16 bit transfers. Our memory chips are 16 bit. however the codecs are 24 bit. And the data that is streaming out of the mcbsps appears to be in 32bit chunks, with the lower bits cleared. I say this because when I look at the bclks there appear to be 32 per d/a channel. I have attached a few screenshots of the issue. The two vertical cursors on the first image represent 32 bits, and channel 1 or the d/a. As you can see the second image shows the bad codec "b channels". The data appears to be shifted by 16 bits. Looking at the last two images you see how they line up when its correct. The resulting sound when bad is like a jack hammer.

As I mentioned before we only have one irq coming in. Int0. It triggers when a chunk of data is available. HOwever, I believe its not just one element, but many samples are ready to be moved. Unless I am reading the setup incorrectly, I dont see how the dma is setup correctly. Especially that it seems to be referneced to int1. But this has be getting ignored somehow because the things does run most of the time and there is never an int1.

Here is the relevant code for setting up the mcbsps and dma:

#pragma CODE_SECTION(GENIIIEMCBSP, ".codez")
void GENIIIEMCBSP()
{
hndlMcbsp1 = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);
hndlMcbsp2 = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);

MCBSP_config(hndlMcbsp1, &mcbspConfig1);
// if (MCBSP_rrdy(hndlMcbsp1))
// MCBSP_read16(hndlMcbsp1);

MCBSP_config(hndlMcbsp2, &mcbspConfig1);
// if (MCBSP_rrdy(hndlMcbsp2))
// MCBSP_read16(hndlMcbsp2);

// MCBSP_start(hndlMcbsp1, MCBSP_XMIT_START | MCBSP_RCV_START | MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 220);
// MCBSP_start(hndlMcbsp2, MCBSP_XMIT_START | MCBSP_RCV_START | MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 220);

}

#pragma CODE_SECTION(GENIIIEIRQ, ".codez")
void GENIIIEIRQ(void)
{
Event1Rcv = DMA_getEventId(hndlDmaRcv1);
// Event2Rcv = DMA_getEventId(hndlDmaRcv2);
Event1Xmt = DMA_getEventId(hndlDmaXmt1);
Event2Xmt = DMA_getEventId(hndlDmaXmt2);
Event3Xmt = DMA_getEventId(hndlDmaXmt3);

IRQ_clear(Event1Rcv);
IRQ_clear(Event1Xmt);
// IRQ_clear(Event2Rcv);
IRQ_clear(Event2Xmt);
IRQ_clear(Event3Xmt);

IRQ_enable(Event1Rcv);
IRQ_enable(Event3Xmt);
// IRQ_enable(Event2Rcv);
IRQ_enable(IRQ_EVT_UART);
IRQ_enable(IRQ_EVT_INT0);
IRQ_globalEnable();

}

#pragma CODE_SECTION(GENIIIEDMA, ".codez")
void GENIIIEDMA(void)
{
volatile Int16 i;
Uint32 addr;

// dmaCfgRcv1.dmacdsal = (DMA_AdrPtr)(((Uint32)(&PagePingInLeft) << 1) & 0xFFFF);
dmaCfgRcv1.dmacdsal = (DMA_AdrPtr)(((Uint32)(&PagePing1) << 1) & 0xFFFF);
// dmaCfgRcv1.dmacdsau = (Uint16)((Uint32)(&PagePingInLeft) >> 15);
dmaCfgRcv1.dmacdsau = (Uint16)((Uint32)(&PagePing1) >> 15);
dmaCfgXmt1.dmacssal = (DMA_AdrPtr)(((Uint32)(&Noise1PingLeft) <<1) & 0xFFFF);
dmaCfgXmt1.dmacssau = (Uint16)((Uint32)(&Noise1PingLeft) >> 15);

// dmaCfgRcv2.dmacdsal = (DMA_AdrPtr)(((Uint32)(&PagePingInLeft) << 1) & 0xFFFF);
// dmaCfgRcv2.dmacdsal = (DMA_AdrPtr)(((Uint32)(&PagePing9) << 1) & 0xFFFF);
// dmaCfgRcv2.dmacdsau = (Uint16)((Uint32)(&PagePingInLeft) >> 15);
// dmaCfgRcv2.dmacdsau = (Uint16)((Uint32)(&PagePing9) >> 15);
dmaCfgXmt2.dmacssal = (DMA_AdrPtr)(((Uint32)(&Noise9PingLeft) <<1) & 0xFFFF);
dmaCfgXmt2.dmacssau = (Uint16)((Uint32)(&Noise9PingLeft) >> 15);
dmaCfgXmt3.dmacssal = (DMA_AdrPtr)(((Uint32)(0x600800) <<1) & 0xFFFF); //&io_control_1 + 0x800
dmaCfgXmt3.dmacssau = (Uint16)((Uint32)(&io_control_1 + 0x800) >> 15);
dmaCfgXmt3.dmacdsal = (DMA_AdrPtr)(((Uint32)(&Noise1PingLeft) <<1) & 0xFFFF);
dmaCfgXmt3.dmacdsau = (Uint16)((Uint32)(&Noise1PingLeft) >> 15);

hndlDmaXmt1 = DMA_open(DMA_CHA0, DMA_OPEN_RESET);
hndlDmaRcv1 = DMA_open(DMA_CHA1, DMA_OPEN_RESET);
hndlDmaXmt2 = DMA_open(DMA_CHA3, DMA_OPEN_RESET);
// hndlDmaRcv2 = DMA_open(DMA_CHA2, DMA_OPEN_RESET);
hndlDmaXmt3 = DMA_open(DMA_CHA4, DMA_OPEN_RESET);
hndlDmaXmt4 = DMA_open(DMA_CHA5, DMA_OPEN_RESET);

// addr = ((Uint32)(io_control_1 + 0x800)) << 1;
// DMA_RSETH(hndlDmaXmt3, DMACSSAL, addr & 0xffff);
// DMA_RSETH(hndlDmaXmt3, DMACSSAU, (addr >> 16) & 0xffff);

DMA_config(hndlDmaXmt1, &dmaCfgXmt1);
DMA_config(hndlDmaRcv1, &dmaCfgRcv1);
DMA_config(hndlDmaXmt2, &dmaCfgXmt2);
// DMA_config(hndlDmaRcv2, &dmaCfgRcv2);
DMA_config(hndlDmaXmt3, &dmaCfgXmt3);
DMA_config(hndlDmaXmt4, &dmaCfgXmt4);

i = DMA_RGETH(hndlDmaRcv1, DMACSR);
i = DMA_RGETH(hndlDmaXmt1, DMACSR);
// i = DMA_RGETH(hndlDmaRcv2, DMACSR);
i = DMA_RGETH(hndlDmaXmt2, DMACSR);
i = DMA_RGETH(hndlDmaXmt3, DMACSR);
i = DMA_RGETH(hndlDmaXmt4, DMACSR);

DMA_RSET(DMAGCR, 0x4);
/*
if(MCBSP_rrdy(hndlMcbsp1))
MCBSP_read16(hndlMcbsp1);

if(MCBSP_rrdy(hndlMcbsp2))
MCBSP_read16(hndlMcbsp2);
*/
// DMA_start(hndlDmaRcv1);
// DMA_start(hndlDmaXmt1);
// DMA_start(hndlDmaXmt2);
}

Here are the structures referenced above.

DMA_Handle hndlDmaXmt1;
DMA_Handle hndlDmaXmt2;
DMA_Handle hndlDmaXmt3;
DMA_Handle hndlDmaRcv1;
DMA_Handle hndlDmaRcv2;
DMA_Handle hndlDmaXmt4;

MCBSP_Handle hndlMcbsp1;
MCBSP_Handle hndlMcbsp2;

//UART_Handle hUart;

#pragma DATA_SECTION(dmaCfgRcv1, ".data1")
static DMA_Config dmaCfgRcv1 =
{
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_EMIF,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_PERIPH,
DMA_DMACSDP_DATATYPE_16BIT //DMA_DMACSDP_DATATYPE_32BIT 8/19/2011
),
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_DBLINDX,
DMA_DMACCR_SRCAMODE_CONST,
DMA_DMACCR_ENDPROG_OFF,
DMA_DMACCR_WP_DISABLE,
DMA_DMACCR_REPEAT_ON,
DMA_DMACCR_AUTOINIT_ON,
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_HI,
DMA_DMACCR_FS_DISABLE,
DMA_DMACCR_SYNC_REVT0
),
DMA_DMACICR_RMK(
DMA_DMACICR_BLOCKIE_ON,
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_OFF,
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_ON,
DMA_DMACICR_TIMEOUTIE_OFF
),
(DMA_AdrPtr)((Uint32)(_MCBSP_DRR10_ADDR<<1)),
0,
NULL,
0,
16, //2,8
(NOISE_BUF>>1),
0,
0,
(-(15*NOISE_BUF - 1)), //1,
NOISE_BUF - 1 //-1
};

#pragma DATA_SECTION(dmaCfgXmt1, ".data1")
static DMA_Config dmaCfgXmt1 =
{
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_PERIPH,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_EMIF,
DMA_DMACSDP_DATATYPE_16BIT //DMA_DMACSDP_DATATYPE_32BIT 8/19/2011
),
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_CONST,
DMA_DMACCR_SRCAMODE_DBLINDX,
DMA_DMACCR_ENDPROG_OFF,
DMA_DMACCR_WP_DISABLE,
DMA_DMACCR_REPEAT_ON,
DMA_DMACCR_AUTOINIT_ON,
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_HI,
DMA_DMACCR_FS_DISABLE,
DMA_DMACCR_SYNC_XEVT0
),
DMA_DMACICR_RMK(
DMA_DMACICR_BLOCKIE_OFF,
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_OFF,
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
),
NULL,
0,
(DMA_AdrPtr)((Uint32)(_MCBSP_DXR10_ADDR<<1)),
0,
16, //2,8
(NOISE_BUF>>1),
(-(15*NOISE_BUF - 1)), //1
NOISE_BUF - 1, //-1
0,
0
};
//Restored 05-JAN-2013
#pragma DATA_SECTION(dmaCfgXmt2, ".data1")
static DMA_Config dmaCfgXmt2 =
{
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_PERIPH,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_EMIF,
DMA_DMACSDP_DATATYPE_16BIT //DMA_DMACSDP_DATATYPE_32BIT
),
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_CONST,
DMA_DMACCR_SRCAMODE_DBLINDX,
DMA_DMACCR_ENDPROG_OFF,
DMA_DMACCR_WP_DISABLE,
DMA_DMACCR_REPEAT_ON,
DMA_DMACCR_AUTOINIT_ON,
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_HI,
DMA_DMACCR_FS_DISABLE,
DMA_DMACCR_SYNC_XEVT1
),
DMA_DMACICR_RMK(
DMA_DMACICR_BLOCKIE_OFF,
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_OFF,
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
),
NULL,
0,
(DMA_AdrPtr)((Uint32)(_MCBSP_DXR11_ADDR<<1)),
0,
16, //2,8
(NOISE_BUF>>1),
(-(15*NOISE_BUF - 1)), //1,
(NOISE_BUF - 1), //-1,
0,
0
};

#pragma DATA_SECTION(dmaCfgXmt3, ".data1")
static DMA_Config dmaCfgXmt3 =
{
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_EMIF,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_EMIF,
DMA_DMACSDP_DATATYPE_16BIT //DMA_DMACSDP_DATATYPE_32BIT 8/19/2011
),
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_POSTINC, //DMA_DMACCR_DSTAMODE_DBLINDX,
DMA_DMACCR_SRCAMODE_POSTINC, //DMA_DMACCR_SRCAMODE_DBLINDX,
DMA_DMACCR_ENDPROG_OFF,
DMA_DMACCR_WP_DISABLE,
DMA_DMACCR_REPEAT_OFF, //DMA_DMACCR_REPEAT_ON
DMA_DMACCR_AUTOINIT_OFF, //DMA_DMACCR_AUTOINIT_ON
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_HI, //DMA_DMACCR_PRIO_HI
DMA_DMACCR_FS_ENABLE, //DMA_DMACCR_FS_DISABLE
DMA_DMACCR_SYNC_NONE //DMA_DMACCR_SYNC_EXTINT0 //
),
DMA_DMACICR_RMK(
DMA_DMACICR_BLOCKIE_ON, //DMA_DMACICR_BLOCKIE_ON
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_OFF, //DMA_DMACICR_FRAMEIE_OFF
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
),
NULL,
0,
NULL, //(DMA_AdrPtr)((Uint32)(_MCBSP_DXR10_ADDR<<1)),
0,
1, //1007 1 2
1004, //1003 1007 1005 1003((NOISE_BUF)>>1) ((NOISE_BUF)>>2) //2
1, //1 45
1,
1, //1
1
};

#pragma DATA_SECTION(dmaCfgXmt4, ".data1")
static DMA_Config dmaCfgXmt4 =
{
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_EMIF,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_EMIF,
DMA_DMACSDP_DATATYPE_16BIT //DMA_DMACSDP_DATATYPE_32BIT 8/19/2011
),
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_POSTINC, //DMA_DMACCR_DSTAMODE_DBLINDX,
DMA_DMACCR_SRCAMODE_POSTINC, //DMA_DMACCR_SRCAMODE_DBLINDX,
DMA_DMACCR_ENDPROG_OFF,
DMA_DMACCR_WP_DISABLE,
DMA_DMACCR_REPEAT_OFF, //DMA_DMACCR_REPEAT_ON
DMA_DMACCR_AUTOINIT_OFF, //DMA_DMACCR_AUTOINIT_ON
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_HI, //DMA_DMACCR_PRIO_HI
DMA_DMACCR_FS_ENABLE, //DMA_DMACCR_FS_DISABLE
DMA_DMACCR_SYNC_NONE //DMA_DMACCR_SYNC_EXTINT0 //
),
DMA_DMACICR_RMK(
DMA_DMACICR_BLOCKIE_ON, //DMA_DMACICR_BLOCKIE_ON
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_OFF, //DMA_DMACICR_FRAMEIE_OFF
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
),
NULL,
0,
NULL, //(DMA_AdrPtr)((Uint32)(_MCBSP_DXR10_ADDR<<1)),
0,
1, //1007 1 2
1004, //1003 1007 1005 1003((NOISE_BUF)>>1) ((NOISE_BUF)>>2) //2
1, //1 45
1,
1, //1
1
};

#pragma DATA_SECTION(mcbspConfig1, ".data1")
static MCBSP_Config mcbspConfig1 = {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF,
MCBSP_SPCR1_RJUST_RZF, //MCBSP_SPCR1_RJUST_LZF,
MCBSP_SPCR1_CLKSTP_DISABLE,
MCBSP_SPCR1_DXENA_NA,
MCBSP_SPCR1_ABIS_DISABLE,
MCBSP_SPCR1_RINTM_RRDY,
0,
MCBSP_SPCR1_RRST_DISABLE
),
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_YES,
MCBSP_SPCR2_SOFT_YES,
MCBSP_SPCR2_FRST_RESET, //MCBSP_SPCR2_FRST_FSG
MCBSP_SPCR2_GRST_RESET, //MCBSP_SPCR2_GRST_CLKG
MCBSP_SPCR2_XINTM_XRDY,
0,
MCBSP_SPCR2_XRST_DISABLE
),
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(15), //(1)(7)
MCBSP_RCR1_RWDLEN1_16BIT //MCBSP_RCR1_RWDLEN1_16BIT
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE,
MCBSP_RCR2_RFRLEN2_OF(0),
MCBSP_RCR2_RWDLEN2_8BIT,
MCBSP_RCR2_RCOMPAND_MSB,
MCBSP_RCR2_RFIG_NO, //MCBSP_RCR2_RFIG_YES,
MCBSP_RCR2_RDATDLY_0BIT
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(15), //(1)(7)
MCBSP_XCR1_XWDLEN1_16BIT //MCBSP_XCR1_XWDLEN1_16BIT
),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE,
MCBSP_XCR2_XFRLEN2_OF(0),
MCBSP_XCR2_XWDLEN2_8BIT,
MCBSP_XCR2_XCOMPAND_MSB,
MCBSP_XCR2_XFIG_NO, //MCBSP_XCR2_XFIG_YES
MCBSP_XCR2_XDATDLY_0BIT
),
MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(1),
MCBSP_SRGR1_CLKGDV_OF(1)
),
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE,
MCBSP_SRGR2_CLKSP_RISING,
MCBSP_SRGR2_CLKSM_CLKS, //MCBSP_SRGR2_CLKSM_INTERNAL
MCBSP_SRGR2_FSGM_DXR2XSR,
MCBSP_SRGR2_FPER_OF(1)
),
MCBSP_MCR1_DEFAULT,
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
MCBSP_PCR_XIOEN_SP,
MCBSP_PCR_RIOEN_SP,
MCBSP_PCR_FSXM_EXTERNAL,
MCBSP_PCR_FSRM_EXTERNAL,
MCBSP_PCR_SCLKME_NO,
0,
MCBSP_PCR_CLKXM_INPUT,
MCBSP_PCR_CLKRM_INPUT,
MCBSP_PCR_FSXP_ACTIVEHIGH,
MCBSP_PCR_FSRP_ACTIVEHIGH,
MCBSP_PCR_CLKXP_FALLING, //MCBSP_PCR_CLKXP_RISING
MCBSP_PCR_CLKRP_RISING
),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};

From our Main section

IRQ_globalDisable();

GENIIIEDMA();

GENIIIEMCBSP();

MCBSP_start(hndlMcbsp1, MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 0x300);
MCBSP_start(hndlMcbsp2, MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 0x300);

DMA_start(hndlDmaRcv1);
DMA_start(hndlDmaXmt1);
DMA_start(hndlDmaXmt2);

MCBSP_start(hndlMcbsp1, MCBSP_XMIT_START | MCBSP_RCV_START, 0);
// MCBSP_start(hndlMcbsp2, MCBSP_XMIT_START | MCBSP_RCV_START, 0);
MCBSP_start(hndlMcbsp2, MCBSP_XMIT_START, 0);

GENIIIEIRQ();

Jackhammer O scope.pdf

0 Cvetolin Shulev-XID over 5 years ago in reply to Glenn Dahl

TI__Guru 65405 points

Glenn,

I have no the same environment to test your issue but I suggest you a tested C code example about McBSP in digital loopback mode and syncs McBSP receive with DMA channel 4 and McBSP transmit with DMA channel 5. Should be useful to test behavior of this example to check McBSP on c55x side.
www.ti.com/tool/sprc133
Download C55XCSL-SPRC133. Start ../C55xxCSL/examples/c5502/csl/dma/dma4

Regards,
Tsvetolin Shulev

0 Glenn Dahl over 5 years ago in reply to Cvetolin Shulev-XID

Prodigy 100 points

I believe I know what you are asking me to do. However, in looking at the example code, attached., I saw exactly the same setup that I have, and I don't understand it, in the context of the demo. Perhaps you can explain this statement on line 183 of the transmit config.

DMA_DMACCR_SYNC_XEVT1

This is the same thing I have in my code. This would imply that the dma starts when the external interrupt 1 triggers. But I couldn't find anywhere where the example that tells you to connect anything external to the ints?

Is this config step overruled by something else?

Is the int actually fired another way, other than externally?

These answers will help me understand how my code is behaving.

main_dma4.c

/*
 * Copyright (C) 2003 Texas Instruments Incorporated
 * All Rights Reserved
 */
/*
 *---------main_dma4.c---------
 * This example places the MCBSP in digital loopback mode and
 * syncs MCBSP receive with DMA channel 4 and MCBSP transmit 
 * with DMA channel 5.                                       
 * The example uses predefined CSL macros and symbolic       
 * constants to create the initialization values needed for  
 * the MCBSP and DMA control registers to effect the transfer
 */
#include <stdio.h>

#include <csl_mcbsp.h>
#include <csl_dma.h>
#include <csl_irq.h>

//---------Global constants---------
#define N       128

//---------Global data definition---------

/* Define transmit and receive buffers */
#pragma DATA_SECTION(xmt,"dmaMem")
Uint16 xmt[N];
#pragma DATA_SECTION(rcv,"dmaMem")
Uint16 rcv[N];


  MCBSP_Config ConfigLoopBack16= {
  MCBSP_SPCR1_RMK(
    MCBSP_SPCR1_DLB_ON,                    /* DLB    = 1 */
    MCBSP_SPCR1_RJUST_RZF,                 /* RJUST  = 0 */
    MCBSP_SPCR1_CLKSTP_DISABLE,            /* CLKSTP = 0 */
    MCBSP_SPCR1_DXENA_NA,                  /* DXENA  = 0 */
    MCBSP_SPCR1_ABIS_DISABLE,              /* ABIS   = 0 */
    MCBSP_SPCR1_RINTM_RRDY,                /* RINTM  = 0 */
    0,                                     /* RSYNCER = 0 */
    MCBSP_SPCR1_RRST_DISABLE               /* RRST   = 0 */
   ),
    MCBSP_SPCR2_RMK(
    MCBSP_SPCR2_FREE_NO,                   /* FREE   = 0 */
    MCBSP_SPCR2_SOFT_NO,                   /* SOFT   = 0 */
    MCBSP_SPCR2_FRST_RESET,                /* FRST   = 0 */
    MCBSP_SPCR2_GRST_RESET,                /* GRST   = 0 */
    MCBSP_SPCR2_XINTM_XRDY,                /* XINTM  = 0 */
    0,                                     /* XSYNCER = N/A */
    MCBSP_SPCR2_XRST_DISABLE               /* XRST   = 0 */
   ),
  MCBSP_RCR1_RMK( 
  MCBSP_RCR1_RFRLEN1_OF(0),                /* RFRLEN1 = 0 */
  MCBSP_RCR1_RWDLEN1_16BIT                 /* RWDLEN1 = 5 */
  ),
 MCBSP_RCR2_RMK(    
    MCBSP_RCR2_RPHASE_SINGLE,              /* RPHASE  = 0 */
    MCBSP_RCR2_RFRLEN2_OF(0),              /* RFRLEN2 = 0 */
    MCBSP_RCR2_RWDLEN2_8BIT,               /* RWDLEN2 = 0 */
    MCBSP_RCR2_RCOMPAND_MSB,               /* RCOMPAND = 0 */
    MCBSP_RCR2_RFIG_YES,                   /* RFIG    = 0 */
    MCBSP_RCR2_RDATDLY_0BIT                /* RDATDLY = 0 */
    ),  
   MCBSP_XCR1_RMK(    
    MCBSP_XCR1_XFRLEN1_OF(0),              /* XFRLEN1 = 0 */ 
    MCBSP_XCR1_XWDLEN1_16BIT               /* XWDLEN1 = 5 */
    
 ),   
 MCBSP_XCR2_RMK(   
    MCBSP_XCR2_XPHASE_SINGLE,              /* XPHASE  = 0 */
    MCBSP_XCR2_XFRLEN2_OF(0),              /* XFRLEN2 = 0 */
    MCBSP_XCR2_XWDLEN2_8BIT,               /* XWDLEN2 = 0 */
    MCBSP_XCR2_XCOMPAND_MSB,               /* XCOMPAND = 0 */
    MCBSP_XCR2_XFIG_YES,                   /* XFIG    = 0 */
    MCBSP_XCR2_XDATDLY_0BIT                /* XDATDLY = 0 */
  ),            
 MCBSP_SRGR1_RMK( 
   MCBSP_SRGR1_FWID_OF(1),                /* FWID    = 1 */
   MCBSP_SRGR1_CLKGDV_OF(1)               /* CLKGDV  = 1 */
 ),   
 MCBSP_SRGR2_RMK(  
    MCBSP_SRGR2_GSYNC_FREE,                /* FREE    = 0 */
    MCBSP_SRGR2_CLKSP_RISING,              /* CLKSP   = 0 */
    MCBSP_SRGR2_CLKSM_INTERNAL,            /* CLKSM   = 1 */
    MCBSP_SRGR2_FSGM_DXR2XSR,              /* FSGM    = 0 */
    MCBSP_SRGR2_FPER_OF(15)                /* FPER    = 0 */
 ),  
 MCBSP_MCR1_DEFAULT,
 MCBSP_MCR2_DEFAULT, 
 MCBSP_PCR_RMK(
   MCBSP_PCR_XIOEN_SP,                     /* XIOEN    = 0   */
   MCBSP_PCR_RIOEN_SP,                     /* RIOEN    = 0   */
   MCBSP_PCR_FSXM_INTERNAL,                /* FSXM     = 1   */
   MCBSP_PCR_FSRM_EXTERNAL,                /* FSRM     = 0   */
   MCBSP_PCR_CLKXM_OUTPUT,                 /* CLKXM    = 1   */
   MCBSP_PCR_CLKRM_INPUT,                  /* CLKRM    = 0   */
   MCBSP_PCR_SCLKME_NO,                    /* SCLKME   = 0   */
   0,                                      /* DXSTAT = N/A   */
   MCBSP_PCR_FSXP_ACTIVEHIGH,              /* FSXP     = 0   */
   MCBSP_PCR_FSRP_ACTIVEHIGH,              /* FSRP     = 0   */
   MCBSP_PCR_CLKXP_RISING,                 /* CLKXP    = 0   */
   MCBSP_PCR_CLKRP_FALLING                 /* CLKRP    = 0   */
 ),
 MCBSP_RCERA_DEFAULT, 
 MCBSP_RCERB_DEFAULT, 
 MCBSP_RCERC_DEFAULT, 
 MCBSP_RCERD_DEFAULT, 
 MCBSP_RCERE_DEFAULT, 
 MCBSP_RCERF_DEFAULT, 
 MCBSP_RCERG_DEFAULT, 
 MCBSP_RCERH_DEFAULT, 
 MCBSP_XCERA_DEFAULT,
 MCBSP_XCERB_DEFAULT,
 MCBSP_XCERC_DEFAULT,
 MCBSP_XCERD_DEFAULT,  
 MCBSP_XCERE_DEFAULT,
 MCBSP_XCERF_DEFAULT,  
 MCBSP_XCERG_DEFAULT,
 MCBSP_XCERH_DEFAULT
};     

DMA_Config  dmaRcvConfig = { 
  DMA_DMACSDP_RMK(
    DMA_DMACSDP_DSTBEN_NOBURST,
    DMA_DMACSDP_DSTPACK_OFF,
    DMA_DMACSDP_DST_DARAMPORT1,
    DMA_DMACSDP_SRCBEN_NOBURST,
    DMA_DMACSDP_SRCPACK_OFF,
    DMA_DMACSDP_SRC_PERIPH,
    DMA_DMACSDP_DATATYPE_16BIT
  ),                                       /* DMACSDP  */
  DMA_DMACCR_RMK(
    DMA_DMACCR_DSTAMODE_POSTINC,
    DMA_DMACCR_SRCAMODE_CONST,
    DMA_DMACCR_ENDPROG_ON,
    DMA_DMACCR_WP_DEFAULT,
    DMA_DMACCR_REPEAT_OFF,
    DMA_DMACCR_AUTOINIT_OFF,
    DMA_DMACCR_EN_STOP,
    DMA_DMACCR_PRIO_LOW,
    DMA_DMACCR_FS_DISABLE,
    DMA_DMACCR_SYNC_REVT1
  ),                                       /* DMACCR   */
  DMA_DMACICR_RMK(
    DMA_DMACICR_AERRIE_ON,
    DMA_DMACICR_BLOCKIE_OFF,
    DMA_DMACICR_LASTIE_OFF,
    DMA_DMACICR_FRAMEIE_ON,
    DMA_DMACICR_FIRSTHALFIE_OFF,
    DMA_DMACICR_DROPIE_OFF,
    DMA_DMACICR_TIMEOUTIE_OFF
  ),                                       /* DMACICR  */
    (DMA_AdrPtr)(MCBSP_ADDR(DRR11)),        /* DMACSSAL */
    0,                                     /* DMACSSAU */
    (DMA_AdrPtr)&rcv,                      /* DMACDSAL */
    0,                                     /* DMACDSAU */
    N,                                     /* DMACEN   */
    1,                                     /* DMACFN   */
    0,                                     /* DMACFI   */
    0                                      /* DMACEI   */
};

DMA_Config  dmaXmtConfig = { 
  DMA_DMACSDP_RMK(
    DMA_DMACSDP_DSTBEN_NOBURST,
    DMA_DMACSDP_DSTPACK_OFF,
    DMA_DMACSDP_DST_PERIPH,
    DMA_DMACSDP_SRCBEN_NOBURST,
    DMA_DMACSDP_SRCPACK_OFF,
    DMA_DMACSDP_SRC_DARAMPORT0,
    DMA_DMACSDP_DATATYPE_16BIT
  ),                                       /* DMACSDP  */
  DMA_DMACCR_RMK(
    DMA_DMACCR_DSTAMODE_CONST,
    DMA_DMACCR_SRCAMODE_POSTINC,
    DMA_DMACCR_ENDPROG_ON,
    DMA_DMACCR_WP_DEFAULT,
    DMA_DMACCR_REPEAT_OFF,
    DMA_DMACCR_AUTOINIT_OFF,
    DMA_DMACCR_EN_STOP,
    DMA_DMACCR_PRIO_LOW,
    DMA_DMACCR_FS_DISABLE,
    DMA_DMACCR_SYNC_XEVT1
  ),                                       /* DMACCR   */
  DMA_DMACICR_RMK(
    DMA_DMACICR_AERRIE_ON,    
    DMA_DMACICR_BLOCKIE_OFF,
    DMA_DMACICR_LASTIE_OFF,
    DMA_DMACICR_FRAMEIE_ON,
    DMA_DMACICR_FIRSTHALFIE_OFF,
    DMA_DMACICR_DROPIE_OFF,
    DMA_DMACICR_TIMEOUTIE_OFF
  ),                                       /* DMACICR  */
    (DMA_AdrPtr)&xmt[1],                      /* DMACSSAL */
    0,                                     /* DMACSSAU */
    (DMA_AdrPtr)(MCBSP_ADDR(DXR11)),       /* DMACDSAL */
    0,                                     /* DMACDSAU */
    N,                                     /* DMACEN   */
    1,                                     /* DMACFN   */
    0,                                     /* DMACFI   */
    0                                      /* DMACEI   */
};

/* Define a DMA_Handle object to be used with DMA_open function */
DMA_Handle hDmaRcv, hDmaXmt;

/* Define a MCBSP_Handle object to be used with MCBSP_open function */
MCBSP_Handle hMcbsp;

volatile Uint16 transferComplete = FALSE;
Uint16 err = 0;
Uint16 old_intm;
Uint16 xmtEventId, rcvEventId;

//---------Function prototypes---------

/* Reference the start of the interrupt vector table */
/* This symbol is defined in file vectors.s55        */
extern void VECSTART(void);

/* Protoype for interrupt functions */
interrupt void dmaXmtIsr(void);
interrupt void dmaRcvIsr(void);
void taskFxn(void);

//---------main routine---------
void main(void)
{
    Uint16 i;

    /* Initialize CSL library - This is REQUIRED !!! */
    CSL_init();

    /* Set IVPH/IVPD to start of interrupt vector table */
    IRQ_setVecs((Uint32)(&VECSTART));

    for (i = 0; i <= N - 1; i++) {  
        xmt[i] =  i + 1;
        rcv[i] = 0;
    }

    /* Call function to effect transfer */
    taskFxn();
}

void taskFxn(void)
{
    Uint16 srcAddrHi, srcAddrLo;
    Uint16 dstAddrHi, dstAddrLo;
    Uint16 i;
 
    /* By default, the TMS320C55xx compiler assigns all data symbols word */
    /* addresses. The DMA however, expects all addresses to be byte       */
    /* addresses. Therefore, we must shift the address by 2 in order to   */
    /* change the word address to a byte address for the DMA transfer.    */ 
    srcAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR(DRR11))) >> 15) & 0xFFFFu;
    srcAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR(DRR11))) << 1) & 0xFFFFu;
    dstAddrHi = (Uint16)(((Uint32)(&rcv)) >> 15) & 0xFFFFu;
    dstAddrLo = (Uint16)(((Uint32)(&rcv)) << 1) & 0xFFFFu;

    dmaRcvConfig.dmacssal = (DMA_AdrPtr)srcAddrLo;
    dmaRcvConfig.dmacssau = srcAddrHi;
    dmaRcvConfig.dmacdsal = (DMA_AdrPtr)dstAddrLo;
    dmaRcvConfig.dmacdsau = dstAddrHi;

	srcAddrHi = (Uint16)(((Uint32)(&xmt[0])) >> 15) & 0xFFFFu;
    srcAddrLo = (Uint16)(((Uint32)(&xmt[0])) << 1) & 0xFFFFu;
    dstAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR(DXR11))) >> 15) & 0xFFFFu;
    dstAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR(DXR11))) << 1) & 0xFFFFu;

    dmaXmtConfig.dmacssal = (DMA_AdrPtr)srcAddrLo;
    dmaXmtConfig.dmacssau = srcAddrHi;
    dmaXmtConfig.dmacdsal = (DMA_AdrPtr)dstAddrLo;
    dmaXmtConfig.dmacdsau = dstAddrHi;


    /* Open MCBSP Port 1 and set registers to their power on defaults */
    hMcbsp = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
    

    /* Open DMA channels 4 & 5 and set regs to power on defaults */
    hDmaRcv = DMA_open(DMA_CHA4,DMA_OPEN_RESET);
    hDmaXmt = DMA_open(DMA_CHA5,DMA_OPEN_RESET);  

    /* Get interrupt event associated with DMA receive and transmit */
    xmtEventId = DMA_getEventId(hDmaXmt);
    rcvEventId = DMA_getEventId(hDmaRcv);
    
    /* Temporarily disable interrupts and clear any pending */
    /* interrupts for MCBSP transmit */
    old_intm = IRQ_globalDisable();
    
    /* Clear any pending interrupts for DMA channels */
    IRQ_clear(xmtEventId);
    IRQ_clear(rcvEventId);

    /* Enable DMA interrupt in IER register */
    IRQ_enable(xmtEventId);
    IRQ_enable(rcvEventId);

    /* Place DMA interrupt service addresses at associate vector */
    IRQ_plug(xmtEventId,&dmaXmtIsr);
    IRQ_plug(rcvEventId,&dmaRcvIsr);

    /* Write values from configuration structure to MCBSP control regs */
    MCBSP_config(hMcbsp, &ConfigLoopBack16); 
    
    /* Write values from configuration structure to DMA control regs */
    DMA_config(hDmaRcv,&dmaRcvConfig);
    DMA_config(hDmaXmt,&dmaXmtConfig);
  
   /* Enable all maskable interrupts */
    IRQ_globalEnable();

    /* Start Sample Rate Generator and Enable Frame Sync */
    MCBSP_start(hMcbsp,
                MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC,
                0x300u);

    /* Enable DMA */
    DMA_start(hDmaRcv);
    DMA_start(hDmaXmt);

    /* Take MCBSP transmit and receive out of reset */
    MCBSP_start(hMcbsp,
                MCBSP_XMIT_START | MCBSP_RCV_START,
                0u);
  
   /* Wait for DMA transfer to be complete */
    while (!transferComplete){
        ;   
    }
   
    /*------------------------------------------*\
     * Compare values 
    \*------------------------------------------*/   
    for(i = 0; i <= N - 1; i++){
        if (rcv[i] != xmt[i]){
            ++err;
            break;
       }
    }

    printf ("%s\n",err?"TEST FAILED" : "TEST PASSED");

    /* Restore status of global interrupt enable flag */
    IRQ_globalRestore(old_intm);
        
    /* We're done with MCBSP and DMA , so close them */
    MCBSP_close(hMcbsp);
    DMA_close(hDmaRcv);
    DMA_close(hDmaXmt);                     
}

interrupt void dmaXmtIsr(void) {
   DMA_stop(hDmaXmt);
   IRQ_disable(xmtEventId);
}

interrupt void dmaRcvIsr(void) {
   DMA_stop(hDmaRcv);
   IRQ_disable(rcvEventId);
   transferComplete = TRUE;
}

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TMS320VC5501: MCBSP setup and dma