Tool/software: TI C/C++ Compiler
Continuing from my thread outlining upgrading from BIOS v5.31.02 to BIOS v5.42.02.10, as per the note on the DSP/BIOS 5.42.02.10 GA Release Notes release notes: "However users *must* rebuild their configuration since the generated linker .cmd file (<prog>cfg.cmd) is different."
I'm getting the following error (a few times over), which in hindsight, I should have expected:
"/BIOS/Dspcfg.cmd", line 294: error: program will not
fit into available memory. placement with alignment fails for section
".log" size 0x18 . Available memory ranges:
ISRAM size: 0x40000 unused: 0x1c max hole: 0x10
As I said in the original thread, I want to avoid changing the code itself and with the original BIOS version, I had only approx 0x2000 free on the IRAM. If I lower the bios.ISRAM.len from 0x40000 to 0x39900 using my original configuration, I get these error messages too. Space-wise, I don't have a lot of wiggle room. And it seems like this new BIOS requires a bit more space.
My question: is there anything on the BIOS side, or compile options that may help me optimize? (I know this is a vague question). I've been looking into breaking up the section .text, (which occupies 0x22400), in the hopes that the linker will be better able to optimize without dealing with this one massive chunk. Would this be a good approach? Does anyone have an alternative idea?
(PS: This may require a separate thread, but are there any inherent risks with filling the L2 Cache so completely? Could this result in weird behavior?)