Tool/software: Linux
Hello all,
We are bringing up a custom board based on am335x icev2 board.But in our custom board we are using DP83867 PHY chip.We are using gpio3[13] pin as PHY_RESETN.While booting we are getting the following error.We have been following other thread with similiar issue but could not find a solution.
[ 1.021586] libphy: Fixed MDIO Bus: probed [ 1.093825] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000 [ 1.101530] davinci_mdio 4a101000.mdio: detected phy mask ffff7fff [ 1.108959] libphy: 4a101000.mdio: probed [ 1.113007] davinci_mdio 4a101000.mdio: phy[15]: device 4a101000.mdio:0f, driver TI DP83867 [ 1.122425] cpsw 4a100000.ethernet: Detected MACID = c4:f3:12:e7:2a:4a [ 1.129232] cpsw 4a100000.ethernet: initialized cpsw ale version 1.4 [ 1.135719] cpsw 4a100000.ethernet: ALE Table size 1024 [ 1.141019] cpsw 4a100000.ethernet: cpts: overflow check period 500 (jiffies) ... ... ... Starting Login Service... [ OK ] Started Job spooling tools. [ OK ] Started RPC Bind Service. [ OK ] Started telnetd.service. [ OK ] Started Network Service. [ 15.336884] net eth0: initializing cpsw version 1.12 (0) [ 15.428150] libphy: PHY 4a101000.mdio:00 not found [ 15.433008] net eth0: phy "4a101000.mdio:00" not found on slave 0, err -19 [ 15.644187] libphy: PHY 4a101000.mdio:01 not found [ 15.649073] net eth0: phy "4a101000.mdio:01" not found on slave 1, err -19 [ 15.961213] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
Following is our dts file configuration:
/* * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ /* * AM335x ICE V2 board * http://www.ti.com/tool/tmdsice3359 */ /dts-v1/; #include "am33xx.dtsi" #include <dt-bindings/net/ti-dp83867.h> / { model = "TI AM3359 ICE-V2"; compatible = "ti,am3359-icev2", "ti,am33xx"; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; chosen { stdout-path = &uart0; }; vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; }; vtt_fixed: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vtt"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; regulator-always-on; regulator-boot-on; enable-active-high; }; leds-iio { status = "disabled"; compatible = "gpio-leds"; led-out0 { label = "out0"; gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out1 { label = "out1"; gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out2 { label = "out2"; gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out3 { label = "out3"; gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out4 { label = "out4"; gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out5 { label = "out5"; gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out6 { label = "out6"; gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out7 { label = "out7"; gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; gpio-decoder { compatible = "gpio-decoder"; gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, <&pca9536 2 GPIO_ACTIVE_HIGH>, <&pca9536 1 GPIO_ACTIVE_HIGH>, <&pca9536 0 GPIO_ACTIVE_HIGH>; linux,axis = <0>; /* ABS_X */ decoder-max-value = <9>; }; }; &am33xx_pinmux { i2c0_pins_default: i2c0_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ >; }; spi0_pins_default: spi0_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */ AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* (C15) spi0_cs1.spi0_cs1 */ AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */ >; }; uart0_pins_default: uart0_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLUP | MUX_MODE0) /* (E16) uart0_txd.uart0_txd */ >; }; uart4_pins_default: uart4_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE1) /* (E18) uart0_ctsn.uart4_rxd */ AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE1) /* (E17) uart0_rtsn.uart4_txd */ >; }; uart1_pins_default: uart1_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* (D16) uart1_rxd.uart1_rxd */ AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) /* (D15) uart1_txd.uart1_txd */ >; }; uart2_pins_default: uart2_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE3) /* (G17) mmc0_clk.uart2_rxd */ AM33XX_IOPAD(0x904, PIN_OUTPUT | MUX_MODE3) /* (G18) mmc0_cmd.uart2_txd */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)/* mii1_txd0.rgmii1_td0 */ AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ AM33XX_IOPAD(0xA34, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (F15) USB1_DRVVBUS.gpio3[13] */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (J16) gmii1_txen.rgmii1_tctl */ AM33XX_IOPAD(0x918, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (J17) gmii1_rxdv.rgmii1_rctl */ AM33XX_IOPAD(0x92c, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (K18) gmii1_txclk.rgmii1_tclk */ AM33XX_IOPAD(0x930, (PIN_INPUT_PULLDOWN | MUX_MODE7)) /* (L18) gmii1_rxclk.rgmii1_rclk */ AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (K17) gmii1_txd0.rgmii1_td0 */ AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (K16) gmii1_txd1.rgmii1_td1 */ AM33XX_IOPAD(0x920, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (K15) gmii1_txd2.rgmii1_td2 */ AM33XX_IOPAD(0x91c, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (J18) gmii1_txd3.rgmii1_td3 */ AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (M16) gmii1_rxd0.rgmii1_rd0 */ AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (L15) gmii1_rxd1.rgmii1_rd1 */ AM33XX_IOPAD(0x938, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (L16) gmii1_rxd2.rgmii1_rd2 */ AM33XX_IOPAD(0x934, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (L17) gmii1_rxd3.rgmii1_rd3 */ AM33XX_IOPAD(0xA34, PIN_OUTPUT_PULLDOWN | MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)) /* mdio_data.mdio_data */ AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0)) /* mdio_clk.mdio_clk */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7)) AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_default>; status = "okay"; clock-frequency = <400000>; tps: power-controller@2d { reg = <0x2d>; }; tpic2810: gpio@60 { compatible = "ti,tpic2810"; reg = <0x60>; gpio-controller; #gpio-cells = <2>; }; pca9536: gpio@41 { compatible = "ti,pca9536"; reg = <0x41>; gpio-controller; #gpio-cells = <2>; }; }; &spi0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins_default>; sn65hvs882@1 { compatible = "pisosr-gpio"; gpio-controller; #gpio-cells = <2>; load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; reg = <1>; spi-max-frequency = <1000000>; spi-cpol; }; spi_nor: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "winbond,w25q64", "jedec,spi-nor"; spi-max-frequency = <80000000>; m25p,fast-read; reg = <0>; partition@0 { label = "u-boot-spl"; reg = <0x0 0x80000>; read-only; }; partition@1 { label = "u-boot"; reg = <0x80000 0x100000>; read-only; }; partition@2 { label = "u-boot-env"; reg = <0x180000 0x20000>; read-only; }; partition@3 { label = "misc"; reg = <0x1A0000 0x660000>; }; }; }; &tscadc { status = "okay"; adc { ti,adc-channels = <1 2 3 4 5 6 7>; }; }; #include "tps65910.dtsi" &tps { vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; vcc3-supply = <&vbat>; vcc4-supply = <&vbat>; vcc5-supply = <&vbat>; vcc6-supply = <&vbat>; vcc7-supply = <&vbat>; vccio-supply = <&vbat>; regulators { vrtc_reg: regulator@0 { regulator-always-on; }; vio_reg: regulator@1 { regulator-always-on; }; vdd1_reg: regulator@2 { regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1326000>; regulator-boot-on; regulator-always-on; }; vdd2_reg: regulator@3 { regulator-name = "vdd_core"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1144000>; regulator-boot-on; regulator-always-on; }; vdd3_reg: regulator@4 { regulator-always-on; }; vdig1_reg: regulator@5 { regulator-always-on; }; vdig2_reg: regulator@6 { regulator-always-on; }; vpll_reg: regulator@7 { regulator-always-on; }; vdac_reg: regulator@8 { regulator-always-on; }; vaux1_reg: regulator@9 { regulator-always-on; }; vaux2_reg: regulator@10 { regulator-always-on; }; vaux33_reg: regulator@11 { regulator-always-on; }; vmmc_reg: regulator@12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; }; &gpio0 { /* Do not idle the GPIO used for holding the VTT regulator */ ti,no-reset-on-init; ti,no-idle-on-init; p7 { gpio-hog; gpios = <7 GPIO_ACTIVE_HIGH>; output-high; line-name = "FET_SWITCH_CTRL"; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_default>; status = "okay"; }; &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; mode-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; //dual_emac = <1>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; compatible = "ti, cpsw-mdio","ti,davinci_mdio"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,min-output-impedence; ti,dp83867-rxctrl-strap-quirk; }; &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; phy-mode = "rgmii-txid"; dual_emac_res_vlan = <1>; }; &cpsw_emac1 { phy_id = <&davinci_mdio>, <1>; phy-mode = "rgmii-txid"; dual_emac_res_vlan = <2>; }; &i2c1{ compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; reg = <0x4802a000 0x1000>; interrupts = <71>; status = "okay"; ad7414@48 { compatible = "analog,ad7414"; reg = <0x48>; status = "okay"; }; }; &elm{ status = "okay"; }; &gpmc { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&nandflash_pins_s0>; ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-xfer-type = "prefetch-dma"; ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <34>; gpmc,adv-wr-off-ns = <44>; gpmc,we-on-ns = <0>; gpmc,we-off-ns = <40>; gpmc,oe-on-ns = <0>; gpmc,oe-off-ns = <54>; gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable. For * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "NAND.SPL"; reg = <0x00000000 0x000020000>; }; partition@1 { label = "NAND.SPL.backup1"; reg = <0x00020000 0x00020000>; }; partition@2 { label = "NAND.SPL.backup2"; reg = <0x00040000 0x00020000>; }; partition@3 { label = "NAND.SPL.backup3"; reg = <0x00060000 0x00020000>; }; partition@4 { label = "NAND.u-boot-spl-os"; reg = <0x00080000 0x00040000>; }; partition@5 { label = "NAND.u-boot"; reg = <0x000C0000 0x00100000>; }; partition@6 { label = "NAND.u-boot-env"; reg = <0x001C0000 0x00020000>; }; partition@7 { label = "NAND.u-boot-env.backup1"; reg = <0x001E0000 0x00020000>; }; partition@8 { label = "NAND.kernel"; reg = <0x00200000 0x00800000>; }; partition@9 { label = "NAND.file-system"; reg = <0x00A00000 0x0F600000>; }; }; };
Murugan S