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Original question:

SMV320C6727B-SP: ESD, I/O Pins, and Emulation Signals

SMV320C6727B-SP: JTAG Timing Parameters

Will Schiller
Prodigy 90 points
Part Number: SMV320C6727B-SP

Hello,

I'm unable to find the SMV320C6727-SP JTAG timing parameters in the datasheet or any of the related literature, such as TMS/TDI setup and hold and min/max TDO delay from TCK.  Where is this information?

Many thanks,

Will S.

  • 0
    TI__Guru 62930 points
    Will,
    I don't see the information either. I suspect that it was not common for this generation of devices, and it was required to meet the hardware guidelines and use supported emulators.
    I am going to do some additional checking, and see if I can point you to some resources.

    Regards,
    Wade
  • 0 in reply to Wade Vonbergen
    TI__Guru 62930 points

    Will,

    I was very fortunate, and was able to locate source data for the timing.

    Parameter                                                MIN  MAX  UNIT

    tc(TCK)        Cycle time, TCK                             35   -   ns

    tsu(TDIV-TCKH) Setup time, TDI/TMS valid before TCK high   10   -   ns

    th(TCKH-TDIV)  Hold time, TDI/TMS valid after TCK high      7   -   ns

    tw­(TRSTL)      Pulse duration, TRSTn low                  100   -   ns

    td(TCKL-TDOV)  Delay time, TCK low to TDO valid             0  15   ns

     

    If this answers your question, please click "Verify it as the answer"
    Regards,
    Wade