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TMS320C5532 or jitter clock

Other Parts Discussed in Thread: TMS320C5532

I am currently working on a project where a DSP and ADC are required.

The potential candidates are the TI TMS320C5532 and Analog Devices AD1974, whose outputs interface to the TMS320C5532 I2S peripherals.

However, we are concerned about the TMS320C5532 I2S clock jitter. The AD1974 data sheet mentions that the ADC clocks should not be pass through a DSP before being applied to the AD1974. We are in the process of characterizing the TMS320C5532 I2S clocks.

Do you have any recommendations on ensuring that the I2S derived clocks’ jitter is kept to a minimum? Should we use jitter cleaners before applying to the ADC?

  • Hi Carlos,

    It is advised to use an ADC that can generate the sampling clocks and transmit clock and frame sync for I2S. In this case the C553x is the I2S slave.

    Refer to Figure 5. ASI Master Mode in the SLAA469 appnote.

    The C55x PLL is precise enough for the digital circuits that depend on it - most crucially the internal Dual-Access RAM (DARAM) that accesses data on both rising and falling clock edges. But with its jitter characteristics and the integer clock dividers, it is not the best clock to supply to an ADC, DAC, or CODEC.

    Also the CLKOUT pin on C553x is not guranteed to be glitch free and should only be used for debugging purposes.

    The PLL on C553x performs with the least jitter (120ps) when PLLOUT = 120MHz. At allowable PLLOUT frequencies above 90MHz, jitter is less than 200ps. I don't have jitter char data for the I2S clocks in master mode (derived from the main PLL).

    The AD1974 datasheet indicates that it can generate clocks from an external crystal. It also appears master mode is supported. See Table 19. AUXPORT Control 1 in the AD1974 data sheet.

    Hope this helps.

    Regards,
    Mark