Tool/software: Code Composer Studio
According the the mcbsp manual, in several places, you can generate a transmit interrupt even when the mcbsp is in reset. This doesn't appear to work. I am trying to trigger a irq whenever the mcbsp sees an external frame sync. I have xint set to 2, which should do that. If I keep the mcbsp in reset I never get the int. If I let the mcbsp run, I get the int on ever new framesync. So I know my interrupt routine and setup is correct.
I need this to work to allow me to kick off the mcbsp properly after the first frame sync has arrived. This is discussed in other resources, where you keep the mcbsp in reset until after the first frame sync arrives, then you start the mcbsp in the isr and the next frame sync kicks off a data transfer correctly.
Below is my code fragments.
hndlMcbsp2 = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
MCBSP_config(hndlMcbsp2, &mcbspConfig1);
#pragma DATA_SECTION(mcbspConfig1, ".data1")
static MCBSP_Config mcbspConfig1 = {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF,
MCBSP_SPCR1_RJUST_RZF, //MCBSP_SPCR1_RJUST_LZF,
MCBSP_SPCR1_CLKSTP_DISABLE,
MCBSP_SPCR1_DXENA_NA,
MCBSP_SPCR1_ABIS_DISABLE,
MCBSP_SPCR1_RINTM_FRM,
0,
MCBSP_SPCR1_RRST_DISABLE
),
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_YES,
MCBSP_SPCR2_SOFT_YES,
MCBSP_SPCR2_FRST_RESET, //MCBSP_SPCR2_FRST_FSG
MCBSP_SPCR2_GRST_RESET, //MCBSP_SPCR2_GRST_CLKG
MCBSP_SPCR2_XINTM_FRM, //MCBSP_SPCR2_XINTM_XRDY
0,
MCBSP_SPCR2_XRST_DISABLE
),
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(15), //(1)(7)
MCBSP_RCR1_RWDLEN1_16BIT //MCBSP_RCR1_RWDLEN1_16BIT
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE,
MCBSP_RCR2_RFRLEN2_OF(0),
MCBSP_RCR2_RWDLEN2_8BIT,
MCBSP_RCR2_RCOMPAND_MSB,
MCBSP_RCR2_RFIG_NO, //MCBSP_RCR2_RFIG_YES,
MCBSP_RCR2_RDATDLY_0BIT
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(15), //(1)(7)
MCBSP_XCR1_XWDLEN1_16BIT //MCBSP_XCR1_XWDLEN1_16BIT
),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE,
MCBSP_XCR2_XFRLEN2_OF(0),
MCBSP_XCR2_XWDLEN2_8BIT,
MCBSP_XCR2_XCOMPAND_MSB,
MCBSP_XCR2_XFIG_NO, //MCBSP_XCR2_XFIG_YES
MCBSP_XCR2_XDATDLY_0BIT
),
MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(1),
MCBSP_SRGR1_CLKGDV_OF(1)
),
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE,
MCBSP_SRGR2_CLKSP_RISING,
MCBSP_SRGR2_CLKSM_CLKS, //MCBSP_SRGR2_CLKSM_INTERNAL MCBSP_SRGR2_CLKSM_CLKS
MCBSP_SRGR2_FSGM_DXR2XSR,
MCBSP_SRGR2_FPER_OF(1)
),
MCBSP_MCR1_DEFAULT,
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
MCBSP_PCR_XIOEN_SP,
MCBSP_PCR_RIOEN_SP,
MCBSP_PCR_FSXM_EXTERNAL,
MCBSP_PCR_FSRM_EXTERNAL,
MCBSP_PCR_SCLKME_NO, //MCBSP_PCR_SCLKME_NO
0,
MCBSP_PCR_CLKXM_INPUT,
MCBSP_PCR_CLKRM_INPUT,
MCBSP_PCR_FSXP_ACTIVEHIGH,
MCBSP_PCR_FSRP_ACTIVEHIGH,
MCBSP_PCR_CLKXP_FALLING, //MCBSP_PCR_CLKXP_RISING
MCBSP_PCR_CLKRP_RISING
),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};
