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AM3352: Power Up Sequence Problem

WU YISYUAN
Expert 2165 points
Part Number: AM3352
Other Parts Discussed in Thread: SN74LVC2G241

hi,

    The power-on sequence on the specifications is as follows:

my test result as below:

I saw MPU start up before 3.3V, what is the impact on the application?

thanks.

  • 0
    TI__Guru**** 393215 points
    Hi,

    This is a violation of the AM335x power-up requirements. It should be corrected.
  • 0
    Expert 2165 points

    Part Number: AM3352

    Hi team,

    As shown below,
    When the I/O has a voltage before the AM3352 starts,
    The normal board power-on sequence will have a VDD_MPU voltage that is established earlier than VDD_3V3A (About 2.8ms earlier).
    But it can start normally.
    What is the timing associated with the internal mechanism of the chip?
    If the VDD_MPU voltage is established earlier than VDD_3V3A, how long does it take for the problem to occur?

    I know that the power-on sequence is abnormal, but I want to know why most products work normally, and only a few products are affected.

    What is the difference within the chip?

    thanks.

  • 0 in reply to WU YISYUAN
    TI__Genius 13567 points

    Please let us know which power management IC you are using.

    It looks like VDD_3V3A is starting as soon as VCC_IN is applied. Is your system intended to do this? If any voltage is applied to the I/O pins of the processor while it is powered off then that may damage the I/O pins and leave them not functional. It's not clear what abnormal behavior you are observing, but could it be related to damaged I/O pins if this is the case?

  • 0 in reply to Ahmad_Rashed
    Expert 2165 points

    Hi Ahmad_Rashed,

                                    thanks for your reply.

                                   I am not use PMIC, my power stage you can reference link as below :

                                  https:// e2e.ti.com/support/processors/f/791/t/791733

                                  In fact, my question is

                                   1.when am3352 is not start up, the I/O pin have high volt about 1.1V, what's the problem with this?

                                   2.As you mentioned, If any voltage is applied to the I/O pins of the processor while it is powered off then that may damage the I/O pins and leave them not functional.
                                     What is the internal mechanism of the chip?

                                   3.If it is a problem caused by Power-Supply Sequencing, is there a definition of how many time intervals will an exception occur?

                                      There are only schematic on the specifications.

    thanks.

  • 0 in reply to Ahmad_Rashed
    Expert 2165 points
    Hi Ahmad_Rashed,
    Any feedback for this question?
    thanks.
  • 0 in reply to WU YISYUAN
    TI__Genius 13567 points

    To prevent voltage applied to the I/O of the AM335x you can use a level translator or a buffer IC. To achieve this on the BeagleBone for example the SN74LVC2G241 is used for the UART console header. This prevents UART activity from harming the AM335x while it is powered off. 

    I saw the power diagram from your other E2E post. Are you using RC delay on the enable pins for the DCDC supplies? What are your connections for RTC PORz and PORz?